© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Lecture 1 An Overview of High-Performance Computer Architecture ECE 463/521 Spring 2006.

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© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Lecture 1 An Overview of High-Performance Computer Architecture ECE 463/521 Spring 2006 Edward F. Gehringer

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Basic Assembly Line Unchangeable truth –It takes a long time to build one car –Example: Time spent in assembly line is 1 hour (12 min. per station) Basic assembly line –Throughput = 1 car per hour –We wait until first car is fully assembled before starting the next one: –  only 1 car in assembly line at a time –  only 1 station is active at a time; other 4 are idle

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Automobile Factory (note: non-animated version) Station 1Station 2Station 3Station 4Station 5 Build frame Connect doors Connect headlights Embed engine Connect wheels & transmission

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Pipelined Assembly Line Unchangeable truth –It still takes a long time to build one car Pipelining –Time to fill pipeline = 1 hour –Once filled, throughput = 1 car per 12 minutes –Speedup due to pipelining is (unusual definition)...

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Simple Processor Pipeline Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Example Instruction ADD r1, r2, r3 –r1  r2 + r3 –IF: Fetch the ADD instruction from memory using the current PC (program counter), then PC  PC + 1 –ID: Decode the ADD instruction to determine the opcode, read values of r2 and r3 from the register file –EX: Perform r2 + r3 in the ALU (arithmetic/logic unit) –MEM: Do nothing (only loads/stores access memory) –WB: Write result of r2 + r3 into r1, in the register file

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Pipeline Performance Problems (1) Data dependences –ADD r1, r2, r3 –SUB r4, r1, r9 –SUB must wait (“stall”) in ID stage until ADD completes ADD writes the result r1 into register file in WB SUB reads the result r1 from register file in ID

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls SUBADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls SUBADD Register file r1 (stalled) Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) r1

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) Register file r1 SUBADD (stalled) (bubble)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) Register file r1 SUBADD (stalled) (bubble)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Dependence Stalls Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) SUB (bubble)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Speedup with data dependences What is the speedup of this pipeline (T sequential /T pipelined ) if 1/10th of all instructions contain a data dependence? Can you give a general formula for a k-stage pipeline? What other information do you need to know?

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Reducing Data Dependence Stalls We could directly forward results from producer to consumer, bypassing the register file. –The hardware is called “data bypass,” “result bypass,” or “register file bypass.” –The technique is called “bypassing” or “forwarding.”

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Bypass ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Bypass SUB Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Bypass SUBADD Register file r1 (garbage) Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Data Bypass r1 (correct) data bypass SUBADD Register file r1 (garbage) Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Pipeline Performance Problems (2) Branches ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 –Which instruction should be fetched after the branch? –IF stage stalls until BEQ reaches EX stage. –EX stage evaluates branch condition (r5 = = r7). “taken”

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Stalls ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Stalls BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Stalls BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD (bubble) ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Stalls Branch outcome: taken BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD (bubble) ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Stalls BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD (bubble) AND ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Reducing Branch Stalls Branch prediction –“Learn” which way a given branch tends to go. –Like predicting the economy, branch prediction is based on past history. –Even simple predictors can be 80% accurate. –If correct: no branch stalls. –In incorrect: “Quash” instructions in previous pipeline stages. Performance degrades to the stall case. May have additional penalties to “clean up” the pipeline.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Prediction (correct) ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (correct)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Predict taken AND Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) BEQADD ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (correct)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Branch Prediction (incorrect) ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 BEQ Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) ADD ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (incorrect)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Predict not taken SUB Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) Write result WB (write- back) BEQADD ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (incorrect)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) LD Write result WB (write- back) SUB Branch outcome: taken BEQ ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (incorrect)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 ADD Stage 1Stage 2Stage 3Stage 4Stage 5 Fetch instruction IF (instruction fetch) Decode & read registers ID (instruction decode) Execute EX (execute) Access memory MEM (memory) LD Write result WB (write- back) SUBBEQAND ADD r1, r2, r3 BEQ X, r5, r7 SUB r4, r1, r9 LD r4, 10(r4) …… X: AND r4, r10, r11 Branch Prediction (incorrect)

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Speedup with branch stalls What is the speedup of the pipeline if 1/5 of the instructions are branches, and 4/5 of those are correctly predicted? Can you give a general formula for a k-stage pipeline? What other information do you need to know?

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Sears Tower Repairman Repair shop is in the basement –Has many tools. –A few are used frequently, e.g., hammer, crescent wrench, screwdriver –Most are used infrequently, e.g., socket wrenches

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Sears Tower Repairman Problem –Sears Tower has 110 stories! –Today, you are working on the top floor. –Can’t bring entire shop with you. –Don’t know exactly which tools to bring with you from the basement.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Sears Tower Repairman Solution –Carry frequently used tools in your tool belt. –Tool-belt becomes a “cache” of tools — drastically reduces the number of trips down to the basement. –When you have to fetch ¼" socket wrench, common sense says to also fetch ½", ¾", etc., just in case.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Caches The processor-memory speed gap –Processor is very fast Intel Pentium-4: 1 GHz, 1 clock cycle = 1 ns –Large memory is slow! Main memory: 50 ns to access, 50 times slower than Pentium-4! –Processor wants large and fast memory. LARGE: O/S and applications consume lots of memory FAST: Otherwise, processor stalls nearly 100% of time waiting for memory.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Caches 256MB Main Memory 50-ns read time Processor 1-ns clock 64KB cache memory 2-ns read time “Hits” 95% of time Tool-belt Basement shop

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Average access time What is the average access time in this memory system?

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Caches Caches are effective because of locality of reference. –Temporal locality: If you access an item, you are likely to access it again in near future. Tool-belt contains frequently used tools. –Spatial locality: If you access an item, you are likely to access a nearby item in the near future. This is why repairman also fetched ½" and ¾" socket wrenches when (s)he only needed ¼".

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Overview of Topics in 463/521 1.Measuring performance and cost 2.Caches and memory hierarchies 3.Instruction-set architecture (ISA) –Defines software/hardware interface 4.Simple pipelining –Data and control (branch) dependences –Data bypasses –Branch prediction

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Overview of Topics in 463/521 5.Complex pipelining and instruction-level parallelism (ILP). –Data hazards –Dynamic instruction scheduling, register renaming, Tomasulo’s algorithm. –Precise interrupts –Superscalar, VLIW, and vector processors.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Projects Three projects –Cache simulator –Branch predictor simulator –Dynamic instruction scheduling pipeline simulator Programming for projects is harder than anything most of you have encountered before.

© 2006 Edward F. Gehringer ECE 463/521 Lecture Notes, Spring 2006 Course Web site These three homepages are linked to a “common” Web site. Any info specific to one course will be listed in the announcements section of that course’s home page.