S04: MSP430 Microarchitecture

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Presentation transcript:

S04: MSP430 Microarchitecture Required: PM: Ch 8.1-3, pgs 109-114 Code: Ch 17, pgs 206-237 Recommended: Wiki: Microarchitecture Wiki: Addressing_mode Wiki: Three-state logic Lab: Microarch Paul Roper

MSP430 Microarchitecture CS 224 Chapter Project Homework S00: Introduction Unit 1: Digital Logic S01: Data Types S02: Digital Logic L01: Warm-up L02: FSM HW01 HW02 Unit 2: ISA S03: ISA S04: Microarchitecture S05: Stacks / Interrupts S06: Assembly L03: Blinky L04: Microarch L05b: Traffic Light L06a: Morse Code HW03 HW04 HW05 HW06 Unit 3: C S07: C Language S08: Pointers S09: Structs S10: I/O L07b: Morse II L08a: Life L09b: Snake HW07 HW08 HW09 HW10 BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Learning Outcomes… After discussing microarchitecture and studying the reading assignments, you should be able to: Explain what is a computer microarchitecture. Describe how memory-mapped I/O is implemented. Program digital I/O using computer ports. List the addressing modes of the MSP430. Identify MSP430 microarchitecture components. Explain how a microarchitecture executes computer instructions. Identify multiplexor, decoder, driver, ALU, and register circuitry. Explain program counter, stack pointer, and condition code registers. Explain the difference between clock cycles and instruction steps. BYU CS 224 MSP430 Microarchitecture Paul Roper

MSP430 Microarchitecture Terms… Absolute Addressing – direct addressing of memory (immutable). Address Space – number of addressable memory locations. Addressability – size of smallest addressable memory location. Arithmetic Logic Unit (ALU) – combinational logic that performs arithmetic and logical operations. Bus – physical connection shared by multiple hardware components. Finite State Machine – finite set of states than transition from a current to next state by some triggering condition. Indexed Addressing – final address is offset added to base address. Instruction Phases – steps used by a FSM to execute an instruction. Memory Mapped I/O – memory locations used to input/output. Microarchitecture – physical implementation of an ISA. Read-Before-Write – access memory before changing with write. Relative Addressing – address is relative to current memory position. BYU CS 224 MSP430 Microarchitecture

Memory Mapped I/O

MSP430 Microarchitecture Memory Mapped I/O Memory Mapped I/O 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Memory Address Bus (A[15:0]) 1 1 Bits A[15:9] Bits A[8:0] 9 to 512 Decoder ... 512 Peripherals Device 0x01ff Device 0x01fe Device 0x0000 High (1) if and only if bits 9-15 are low (0). Memory CS High (1) if any of bits 9-15 are high (1). BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Memory Mapped I/O MSP430 P1/P2 Port Registers 0xFFFF Memory Mapped I/O Ports connect CPU to external world Ports are 8 bit memory locations (R/W enabled) Each bit independently programmable for Input or Output (I/O) Edge-selectable input interrupt capability (P1/P2) O I 0xF800 0x0A00 P1DIR 0x0022 0000 0000 P1OUT 0x0021 P1IN 0x0020 bis.b #0x21,&P1DIR bis.b #0x01,&P1OUT 0x0200 0010 0001 0000 0001 0010 0000 xor.b #0x01,&P1OUT 0x0000 MSPG2553 BYU CS 224 MSP430 Microarchitecture

Digital Port Input/Output Memory Mapped I/O Digital Port Input/Output Direction Register (PxDIR): Bit = 0: the individual port pin is set as an input (default) Bit = 1: the individual port pin is set as an output Input Register (PxIN): Bit = 1: The input port pin is high Bit = 0: The input port pin is low Output Register (PxOUT): Bit = 1: The output port pin is set high; Bit = 0: The output port pin is set low. Note: the PxOUT is a read-write register which means previously written values can be read, modified, and written back BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Quiz 4.1 Four LEDs are attached to Port 4, bits 0 thru 3. Indicate which LEDs are ON/OFF/Undefined after each instruction to the left is executed. P4.3 P4.2 P4.1 P4.0 mov.b #0x0f,&P4DIR and.b #0xf0,&P4OUT bis.b #0x09,&P4OUT xor.b #0x0f,&P4OUT bic.b #0x06,&P4OUT add.b #0x03,&P4OUT BYU CS 224 MSP430 Microarchitecture

Microarchitecture

Microarchitecture Journey Finite State Machine ISA Register we d q a1 a0 2-to-4 Decoder 4-to 1 Multiplexor Storage Devices Microarchitecture Sequential Logic q d we W X Y Z A B S C Combinational Logic a b NOR Complementary Logic Transistor BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture The Instruction Set Architecture (ISA) defines the processor instruction set, processor registers, address and data formats The processor as seen by an assembly language programmer. The microarchitecture implements the ISA. Gates, registers, ALUs, clocks Data and control paths Microarchitectures differentiate themselves by: Chip area/cost Power consumption Logic complexity Manufacturability Ease of debugging Testability BYU CS 224 MSP430 Microarchitecture

Lab 4: MSP430 Microarchitecture MSP430 Microarchitecture Simulator: Use the MSP430 Microarchitecture Simulator to create a machine that implements the Texas Instruments MSP430 ISA. Generate a Finite State Machine (FSM) for fetch, decode, evaluate source, evaluate destination, execute, and store cycles of MSP430 instructions. Execute a program that displays an incrementing counter in the simulator LEDs. Learning Objectives: Learn how a microarchitecture executes computer instructions. Learn about multiplexor, decoder, driver, ALU, and register circuitry. Learn about program counter, stack pointer, and condition code registers. Understand better the difference between clock cycles and instruction steps. BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture MSP430 Machine Code ;************************************************************** ; MSP430 Micro-Architecture Simulator Code ; ; Description: Display an incrementing counter in LEDs. .cdecls C,"msp430.h" .text 8000: 4031 0600 RESET: mov.w #0x0600,SP ; Init stack pointer 8004: 40b2 5a80 0120 mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT 800a: d0f2 000f 0022 bis.b #0x0f,&P1DIR ; Set P1.0-3 output 8010: 430e mov.w #0,r14 8012: 4ec2 0021 loop: mov.b r14,&P1OUT ; output P1.0-3 8016: 531e add.w #1,r14 8018: f03e 000f and.w #0x000f,r14 ; mask counter 801c: 401f 0003 mov.w delay,r15 ; Delay to R15 8020: 120f push r15 8022: 8391 0000 wait: sub.w #1,0(sp) ; decrement delay count 8026: 23fd jnz wait ; delay over? 8028: 41ef mov.w @sp+,r15 ; y 802a: 3ff3 jmp loop ; repeat 802c: 0002 delay: .word 2 .sect ".reset" ; MSP430 RESET Vector .word RESET ; NMI .end BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Simulator BYU CS 224 MSP430 Microarchitecture

MSP430 Instruction Cycles

MSP430 Instruction Cycles MSP430 Clock Cycles MSP430 Instruction Cycles Data being sent/received on the data bus is called a cycle. 1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode 1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes +2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory Additionally +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles A bus is characterised by the amount of information that can be transmitted at once. This amount, expressed in bits, corresponds to the number of physical lines over which data is sent simultaneously. A 32-wire ribbon cable can transmit 32 bits in parallel. The term "width" is used to refer to the number of bits that a bus can transmit at once. Additionally, the bus speed is also defined by its frequency (expressed in Hertz), the number of data packets sent or received per second. Each time that data is sent or received is called a cycle. BYU CS 224 MSP430 Microarchitecture Paul Roper

MSP430 Microarchitecture Quiz 4.2 Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay? ? DELAY .equ mov.w #DELAY,r12 ; 2 cycles delay1: mov.w #1000,r15 ; 2 cycles delay2: sub.w #1,r15 ; 1 cycle jne delay2 ; 2 cycles sub.w #1,r12 ; 1 cycle jne delay1 ; 2 cycles BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture

MSP430 Microarchitecture Control Logic (Finite State Machine) Memory (Address Space) Clocks MSP430 MPU 16 16-bit Registers Input/Output ALU BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Quiz 4.3 Match the following terms: ALU Clocks Control I/O Memory Peripherals Registers Address space Execution speed External devices Fast memory Finite State Machine Memory mapped Word length BYU CS 224 MSP430 Microarchitecture

Not all instructions require all six phases Instruction Cycle The Instruction Cycle INSTRUCTION FETCH Obtain the next instruction from memory DECODE Examine the instruction, and determine how to execute it SOURCE OPERAND FETCH Load source operand DESTINATION OPERAND FETCH Load destination operand EXECUTE Carry out the execution of the instruction STORE RESULT Store the result in the designated destination Not all instructions require all six phases BYU CS 224 MSP430 Microarchitecture

Fetching an Instruction Fetch Cycle Fetching an Instruction  PC can be incremented anytime during the Fetch phase  PC BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes Addressing Modes The MSP430 has four basic addressing modes: 00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect (source only) 11 = @Rs+ - Indirect Auto-increment (source only) When used in combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+ (source only) BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Quiz 4.4 Match the following source operand modes: add.w tab(r10),r9 and.w &mask,r12 bis.b #0x08,r6 mov.b cnt,r11 mov.w r4,r5 mov.w #100,r14 sub.w @r4+,r5 xor.b @r8,r15 Absolute Constant Immediate Indexed register Indirect auto-increment Indirect register Register Symbolic BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes Addressing Mode Demo 8000: 540A 8002: 541A 0006 8006: 542A 8008: 543A 800a: 501A 81f4 800e: 521A 0200 8012: 503A 0064 8016: 531A 8018: 1210 0004 801c: 3ff1 .text start: add.w r4,r10 ; r4 += r10; add.w 6(r4),r10 ; r10 += M[r4+6]; add.w @r4,r10 ; r10 += M[r4]; add.w @r4+,r10 ; r10 += M[r4++]; add.w cnt,r10 ; r10 += cnt; add.w &cnt,r10 ; r10 += cnt; add.w #100,r10 ; r10 += 100; add.w #1,r10 ; r10++; push cnt ; M[--r1] = cnt; jmp start BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 00 = Register Mode add.w r4,r10 ; r10 += r4 Address Bus Memory CPU PC Data Bus (1 cycle) 0x540a PC IR Registers +2 0x540a PC R4 ADDER R10 ALU BYU CS 224 MSP430 Microarchitecture

Source: Register Mode – Rs Evaluate Source Operand Source: Register Mode – Rs Select the source register  Rs BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 01 = Indexed Mode add.w 6(r4),r10 ; r10 += M[r4+6] Address Bus Memory CPU PC Data Bus (1 cycle) 0x541a PC IR Registers +2 +2 0x541a PC PC 0x0006 Data Bus (+1 cycle) R4 ADDER Address Bus R10 Data Bus (+1 cycle) ALU BYU CS 224 MSP430 Microarchitecture

Source: Indexed Mode – x(Rs) Evaluate Source Operand Source: Indexed Mode – x(Rs)   Rs  PC  PC PC incremented at end of phase Use PC to obtain index, use Rs for base register BYU CS 224 MSP430 Microarchitecture

10 = Indirect Register Mode Addressing Modes 10 = Indirect Register Mode add.w @r4,r10 ; r10 = M[r4] Address Bus Memory CPU PC Data Bus (1 cycle) 0x542a Registers PC IR +2 0x542a PC R4 Address Bus ADDER R10 Data Bus (+1 cycle) ALU BYU CS 224 MSP430 Microarchitecture

Source: Indirect Mode – @Rs Evaluate Source Operand Source: Indirect Mode – @Rs   Rs BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 11 = Indirect Auto-increment Mode add.w @r4+,r10 ; r10 += M[r4++] Address Bus Memory CPU PC Data Bus (1 cycle) 0x543a Registers PC IR +2 0x543a PC Address Bus 0002 R4 ADDER R10 Data Bus (+1 cycle) ALU BYU CS 224 MSP430 Microarchitecture

Source: Indirect Auto Mode – @Rs+ Evaluate Source Operand Source: Indirect Auto Mode – @Rs+   Rs Increment by 1 (.b) or 2 (.w) BYU CS 224 MSP430 Microarchitecture

*Also called PC Relative address mode Addressing Modes 01 w/R0 = Symbolic Mode add.w cnt,r10 ; r10 += M[cnt] Address Bus Memory CPU PC Data Bus (1 cycle) 0x501a PC IR Registers +2 +2 0x501a PC PC PC 0x000c Data Bus (+1 cycle) ADDER Address Bus cnt R10 Data Bus (+1 cycle) ALU *Also called PC Relative address mode BYU CS 224 MSP430 Microarchitecture

Source: Symbolic Mode – label Evaluate Source Operand Source: Symbolic Mode – label   PC  PC  PC PC incremented at end of phase Use PC to obtain relative index and for base register BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Quiz 4.5 Present the destination operand of the following instruction to the ALU: add.w r4,cnt ; M[cnt] += r4 Memory CPU PC IR Registers PC 0x5480 PC PC PC 0x5480 0x0218 R4 ADDER cnt ALU BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 01 w/R2 = Absolute Mode add.w &cnt,r10 ; r10 += M[cnt] Address Bus Memory CPU PC Data Bus (1 cycle) 0x521a Registers PC IR +2 +2 0x521a PC PC 0xc018 Data Bus (+1 cycle) 0000 ADDER Address Bus cnt R10 Data Bus (+1 cycle) ALU BYU CS 224 MSP430 Microarchitecture

Source: Absolute Mode – &Address Evaluate Source Operand Source: Absolute Mode – &Address   #0  PC PC can be incremented anytime during the phase Use PC to obtain absolute address, use #0 for base register BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 11 w/R0 = Immediate Mode add.w #100,r10 ; r10 += 0x0064 Address Bus Memory CPU PC Data Bus (1 cycle) 0x503a PC IR Registers +2 +2 0x503a PC PC 0x0064 Data Bus (+1 cycle) ADDER R10 ALU BYU CS 224 MSP430 Microarchitecture

Source: Immediate Mode – #n Evaluate Source Operand Source: Immediate Mode – #n  PC can be incremented anytime during the phase  PC BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Evaluate Source Operand MSP430 Source Constants To improve code efficiency, the MSP430 "hardwires" six register/addressing mode combinations to commonly used source values: #0 - R3 in register mode (00) #1 - R3 in indexed mode (01) #2 - R3 in indirect mode (10) #-1 - R3 in indirect auto-increment mode (11) #4 - R2 in indirect mode (10) #8 - R2 in indirect auto-increment mode (11) Eliminates the need to use a memory location for the immediate value - commonly reduces code size by 30%. BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes Constant Generator add.w #1,r10 ; r10 += 1 Address Bus Memory CPU PC Data Bus (1 cycle) 0x531a PC IR Registers +2 0x531a PC 0000 0001 0002 0004 0008 ffff ADDER R10 ALU BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Evaluate Source Operand Constant Mode – #{-1,0,1,2,4,8}  R3 BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes 3 Word Instruction add.w cnt,var ; M[var] += M[cnt] Address Bus Memory CPU PC Data Bus (1 cycle) 0x5090 Registers PC IR +2 +2 +2 0x5090 PC PC PC PC 0x000c Data Bus (+1 cycle) 0x0218 Data Bus (+1 cycle) ADDER Address Bus cnt Address Bus Data Bus (+1 cycle) Data Bus (+1 cycle) var ALU Data Bus (+1 cycle) BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Quiz 4.6 Show how to retrieve a PC-relative destination operand from memory and present to the ALU: BYU CS 224 MSP430 Microarchitecture

Final Instruction Phases Execute PUSH Decrement stack pointer (R1) Ready address for store phase JUMP Compute 10-bit, 2’s complement, sign extended Add to program counter (R0) Store Move data from ALU to register, memory, or I/O port BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Execute Phase Push Instruction push.w cnt ; M[--sp] = M[cnt] Address Bus Memory CPU PC Data Bus (1 cycle) 0x1210 Registers PC IR +2 +2 0x1210 PC PC PC fffe 0x000c Data Bus (+1 cycle) SP Address Bus (+1 cycle) ADDER Address Bus cnt 0xa5a5 Data Bus (+1 cycle) SP SP Data Bus (+1 cycle) 0xa5a5 ALU BYU CS 224 MSP430 Microarchitecture

Use Store Phase to push on stack Execute Cycle Execute Phase: PUSH.W  SP SP = SP - 2 Use Store Phase to push on stack BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Addressing Modes Execute Phase: jne func jne func ; pc += sext(IR[9:0]) << 1 Address Bus Memory CPU PC Data Bus (1 cycle) 0x3c2a Registers PC IR +2 0x3c21 PC SEXT[9:0]<<1 R2 ADDER COND Jump Next func ALU BYU CS 224 MSP430 Microarchitecture

Select “COND” to conditionally change PC 2’s complement, sign-extended Execute Cycle Execute Phase: Jump  PC Select “COND” to conditionally change PC 2’s complement, sign-extended BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Store Cycle Store Phase: Rd  BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture Store Cycle Store Phase: Other…  BYU CS 224 MSP430 Microarchitecture

MSP430 Microarchitecture BYU CS 224 MSP430 Microarchitecture