Irradiation results K.Røed, D.Röhrich, K. Ullaland, B. Pommeresche University of Bergen, Norway B.Skaali, J.Wikne, E.Olsen University of Oslo, Norway V.Lindenstruth, H.Tilsner, S.Martens, D. Gottschalk KIP, University of Heidelberg, Germany U. Kebschull, G. Tröger KIP, University of Heidelberg, Germany M. Stockmaier Physikalisches Institut, University of Heidelberg L.Musa, H. Müller CERN 1.Radiation effects 2.Test setup 3.Cross section measurement 4.TPC Readout Controller Unit 5.TPC radiation tolerance scheme 6.TRD/TPC DCS 7.PHOS FEE

1. Radiation effects K.Røed, D.Röhrich, K. Ullaland, B. Pommeresche University of Bergen, Norway B.Skaali, J.Wikne, E.Olsen University of Oslo, Norway V.Lindenstruth, H.Tilsner, S.Martens, D. Gottschalk KIP, University of Heidelberg, Germany U. Kebschull, G. Tröger KIP, University of Heidelberg, Germany M. Stockmaier Physikalisches Institut, University of Heidelberg L.Musa, H. Müller CERN

3 Radiation effects in semiconductors Single Event Effects (SEE) –Stochastic process –E.g. soft errors (upsets) in SRAM FPGA –Measurement: cross section (per bit, per device) [cm 2 ] for bit-flip under irradiation Radiation damage –Cumulative effect –Deterioration of performance, sometimes threshold behaviour –Measurement: performance as function of fluence or dose –Dose of 63 MeV protons at a fluence of protons/cm 2 /s in silicon semiconductors: 140 Gy = 14 krad –Dose of 25 MeV protons at a fluence of protons/cm 2 /s in silicon semiconductors: 280 Gy = 28 krad

4 Single Event Upset (SEU) High-energetic hadrons induce nuclear reactions in the silicon (E > 20 MeV - protons, neutrons, pions, kaons) Intermediate energy neutrons (2 MeV < E < 20 MeV) contribute little (10%) to SEUs (Almost) no effect due to thermal neutrons Heavy recoil ions from reactions ionize the material Charge deposition leads to a change in state of a transistor (SEU) Soft error – can be corrected (rewriting or reprogramming) Si(p,2p)Al Si(p,p  )Mg Si(n,p)Al Si(n,  )Mg Si p

5 Upset detection in FPGAs SEU –Upset in configuration SRAM –Measured by reading back configuration bitstream SEFI –Single Event Functional Interrupt –Upset in design Ratio SEU/SEFI  4 – 10 –Routing:  90% of resources –Application: 90-98% of config cells are not used

6 ● Two types of concern ● Upsets in configuration SRAM cells ● Single bitflips in register elements ● The APEX20K400E offers no direct readout of configuration SRAM ● Indirectly detection of configuration upset through the VHDL design ● Error observed reflects a change in logic due to a configuration upset, and not the configuration upset itself ● A fixed pattern is shifted through and compared for setups when read out Upset detection in ALTERA FPGAs Serial Slow Control Network SCSN FPGA Data in Data out Serial Slow Control Network SCSN

7 FIFO in internal RAM Shiftregister in logic elements Example of analyzing data Single upset Configuration upset

2. Test setup

9 Test setup (1) Oslo Cyclotron –25 and 28 MeV external proton beam –flux ~ 10 7 – 10 8 protons/s cm² –Flux measurements: Uranium fission target + TFBC –Intensity monitor: faraday cup –Beam profile: spot 1.5cm x 1.5cm

10 Test setup (2) TSL (Uppsala) –Proton beam »38 and 180 MeV external proton beam »flux ~ 10 7 – 10 8 protons/s cm² »flux measurements: Uranium fission target + TFBC »intensity monitor: scattered protons -> scintillator »beam profile:  3cm –Neutron beam »large beam spot

3. Cross section measurements

12 Results (1) APEX20k400 –SEFI - shift register design K. Røed, Master thesis, UiB, 2004

13 Results (2) APEX20k400 –Energy dependence of cross section –CS = 6.0 x  1.1 x cm 2 (E >30 MeV)

14 Results (3) Energy dependence of cross section - comparison to simulations

15 Results (4) ALTERA EPXA1F484C1 - ARM See S. Martens, Diploma thesis, KIP (2003) 28 MeV (protons/s cm 2 ) Mean time between failures (s) cross section (cm 2 ) 3 x x x x x x 10 -9

16 Cross section results – summary (1) Cross section [cm 2 ] APEX20k x  1.1 x APEX20k60E1.6 x (ref.: DAQ TDR) EPXA1F484C12 x (scaled to E > 60 MeV) EP1C20 (Cyclone)3.3 * (neutrons, ref.: IROC) SEFI CS for Altera devices

17 Cross section results – summary (2) SEFI and SEU CS for Xilinx devices device  (SEFI) per device  (SEU) per device XC2VP7 – Virtex II-Pro2 * (scaled to E > 60 MeV) 5 * (scaled to E > 60 MeV) XC2V3000 – Virtex II (neutrons, ref.: IROC) 8.2 * * XC3S Spartan (neutrons, ref.: IROC) 2.3 * * XC3S Spartan (protons, ref.: Xilinx) 5.6 * XC2VP4 – Virtex II-Pro (protons, ref.: Xilinx) 1.6 x 10 -7

18 Cross section results – summary (3) SEU CS per bit for Xilinx technologies

4. TPC Readout Controller Unit

20 Radiation levels – simulation (1) Georgios Tsiledakis, GSI

21 Radiation levels – simulation (2) Georgios Tsiledakis, GSI

22 Radiation levels – simulation (3) Georgios Tsiledakis, GSI

23 Radiation levels – simulation (4) Comparison to ALICE-INT –Difference in flux of factor 2 –790 Hz (averaged of all z) vs 384 Hz (absorber side, worst case)

24 Cross section results - reminder Cross section [cm 2 ] RCU FPGA – APEX20K x  1.1 x SIU – APEX20K601.6 x DCS – EPXA12 x 10 -9

25 Error estimates per run Errors per run (4 hours) per TPC system RCU3.7 SIU1.0 DCS1.9 SEUs in RCU main FPGA Errors per run (4 hours)

26 Conclusion (1) SRAM based FPGAs –Error rate is so low that one can cope with it – if SEUs can be detected instantenously or FPGA can be reconfigured in real-time –ALTERA FPGAs do not provide real-time readback of configuration data nor disclose format of bitstream –Better choice: XILINX Virtex-IIPro FPGAs »Real-time (= while running) readback of configuration data for verification »Partial reconfiguration while running »Existing infrastructure, running under linux (e.g. on DCS board), allowing full and high level control of the FPGA internals while running »Radiation tolerant scheme: see next chapter

27 Conclusion (2) Fallback solution: FLASH based FPGA (Actel) –ProASIC Plus FLASH Family FPGAs –Preliminary irradidation results »Device: APA075 »Test method: reading back configuration »Failure (probably latch-up) after a fluence of 3.7x protons/cm 2  dose of 1000 Gy »Expected dose in 10 years of ALICE: ~ 5.7 Gy

28 Next steps Develop radiation tolerance strategy (see chapter 8)  Decide to migrate RCU-FPGA to XILINX  Select appropriate device w.r.t. resources (e.g. number of I/O cells)  Decide to keep DCS board unchanged  Keep Actel-FPGA as fallback solution  Port RCU design to new develop environment Port existing reconfiguration scheme to DCS board Verify expected performance under irradiation –XILINX OCL in August  –System TSL in fall with large beam spot (  30cm)

29 Radiation test of RCU components (1)

30 Radiation test of RCU components (2) Example: GTL bus transceiver 10 y ALICE

31 Radiation test of RCU components (3) Summary 10 y ALICE

5. Radiation tolerance scheme V.Lindenstruth, U. Kebschull, G. Tröger KIP UiB, UiO

33 FPGAs: Active Reconfiguration for Radiation Tolerance Gerd Tröger Technische Informatik Universität Leipzig

34 Active Partial Reconfiguration Most commonly: full configuration only, device reset Active Partial Reconfiguration: ca. 6-8 years, since Virtex series, uninterrupted operation –Configuration Space divided into units, “frames” in Xilinx terminology –‘Partial’: frames are individually reconfigurable –‘Active’: without interrupting the device, glitch-free: no change → no signal flanks –Configuration is ‘atomic operation’ (no bit shifting)

35 Configuration Frames

36 Radiation Tolerance FPGAs: configuration plane = big memory → particularly radiation sensitive Normal Approach (ASICs): Hamming Codes for registers, TMR (triple module redundancy) for critical components Not practical for the configuration plane: too expensive for normal COTS FPGAs –→ Upset Mitigation by Refresh –→ Active Partial Reconfiguration feature used to continuously ‘repair’ the FPGA configuration Alternative: special FPGAs ($$$)

37 Preliminary Test Results SEFI test with Xilinx Virtex-II Pro FPGA reconfiguration started after 200 seconds: errors are corrected continuously

38 Preliminary Conclusions Test conditions –Flux = 3.7 x protons/cm 2 /s –Reconfiguration time = 5 s Real life –Flux = 7.9 x 10 2 hadrons/cm 2 /s –Reconfiguration time = 10 ms Duty cycle: times better in real life

39 Target System Implementation (1) FPGA on RCU board External SelectMAP configuration interface (8 bit parallel, 50/66 MHz); alternatively JTAG (~5 MBit/s) Rad-Hard controller + memory for reconfiguration Alternatively: non rad-hard controller, ‘best effort’ strategy –expected individual upset rates (1 per 400 hours) and downtime (approx. ~ controller reboot time: 10 sek.) are low enough to justify this approach

40 Target System Implementation (2) FPGA on RCU –Reconfigured via RCU bus DCS FPGA running Linux provides tool –ICAP: “Internal Configuration Access Port” –internal equivalent of the SelectMAP interface –Linux driver –FPGA virtual file system fpga/ phys.resource/app.core/platform/ region1/region2/ mycore.bit mycore.sym config R1 R2 R3 R4

6. TRD DCS board K.Røed, D.Röhrich, K. Ullaland, B. Pommeresche University of Bergen, Norway B.Skaali, J.Wikne, E.Olsen University of Oslo, Norway V.Lindenstruth, H.Tilsner, S.Martens, D. Gottschalk KIP, University of Heidelberg, Germany U. Kebschull, G. Tröger KIP, University of Heidelberg, Germany M. Stockmaier Physikalisches Institut, University of Heidelberg L.Musa, H. Müller CERN

42 DCS Board Production Readiness Review Dirk Gottschalk Holger Höbbel Volker Kiworra Tobias Krawutschke Volker Lindenstruth Stefan Martens Vojtech Petracek Marc R. Stockmeier Heinz Tilsner Chair of Computer Science and Engineering / Prof. Dr. Volker Lindenstruth / January 2004 Project Link : page 42http:// Board Version 1.16 Sept./ Oct. 2003

43 Page 43 DCS Board Production Readiness Review DCS board schematic overview.

44 Total Dose in 10 ALICE years (ALICE-INT ) TPC: 16 Gy  5 x 10 9 protons/cm 25 MeV  pA  nA TRD: 1.8 Gy  5 x 10 8 protons/cm 25 MeV

45 DCS Board Production Readiness Review Device TypeDevice NameManufact.PartikelsResultsby / at FPGAEPXA1F484-C3AlteraProtonssee plots below1*) ARM CoreEPXA1F484-C3AlteraProtonssee plots below1*) Flash EPROMMX29LV320BTC-70MacronixProtonssee plots below1*) SDRAMMT48LC16C16A2MicronProtonssee plots below1*) CPLDsLC4032ZC-75T48LatticeProtonssee results below1*) Ethernet PhyLXT971ALCIntelProtonssee results below1*) ADCAD7708BRUADProtonssee plots below1*) OptocouplersLTV357TLiteonProtonssee results below1*) Voltage Ref.AD1582ARTADtbd Charge PumpREG711EA-5BB/TItbd LVDS DriverSN75LVDT390PWTIProtonssee results below1*) LVDS Receiv.SN75LVDS391PWTIProtonssee results below1*) Page 45 Radiation Beamtest Results (1) : *1) D. Gottschalk/KIP, S. Martens/KIP, M. Stockmeier/PI, P. Struck/KIP, H. Tilsner/KIP at University of OSLO November 2003 *2) L. Musa / CERN made rad tests as well at CERN and University of OSLO. *3) Links provide documents for details.

46 DCS Board Production Readiness Review Radiation Beamtest Results (2) : Device TypeDevice NameManufact.PartikelsResults *3) by / at RS422 DriverAM26LV31CTItbd RS422 Receiv.AM26LV32CTItbd WatchdogTPS DGKTItbd Voltage 3V3MIC BU or LP3962ES-3.3 Micrel NS Protonssee plots below/ *2) Voltage 1V8MIC BU or LP3962ES-1.8 Micrel NS Protonssee plots below/ *2) OptolinkTRR-1B43TruelightProtons, Gamma, NeutronsOkay / doc.pdfGastal / Moreira / CERN OptolinkHFBR-2316TAgilentProtons, Gamma, NeutronsOkay / doc.pdfGastal / Moreira/ CERN PLL Clock RecoveryTTCrx 3.2CERN??okay / CERN *1) D. Gottschalk/KIP, S. Martens/KIP, M. Stockmeier/PI, P. Struck/KIP, H. Tilsner/KIP at University of OSLO November 2003 *2) L. Musa / CERN made rad tests at CERN and University of OSLO. *3) Links provide documents for details. Page 46

47 DCS Board Production Readiness Review Radiation Beamtest Plots : 256Mb SDRAM Micron MT48LC16M16 SDRAM Beam Test Plot Page 47 Test plots by Stephan Martens Diploma Thesis MB used for test Error rate : 1 error per ALICE year per 16MB

48 DCS Board Production Readiness Review Radiation Beamtest Plots : Flash EPROM Beam Test Plot Page 48 Test plots by Stephan Martens Diploma Thesis 2003 First error after 146 x 10 ALICE years 1nA Beam current

49 DCS Board Production Readiness Review Radiation Beamtest Plots : Altera EPXA1 FPGA EPXA1 FPGA Beam Test Plot Page 49 Test plots by Stephan Martens Diploma Thesis 2003 Design : „Coprozessor“ with full FPGA usage.

50 DCS Board Production Readiness Review Radiation Beamtest Plots : Altera EPXA1 ARM core EPXA1 ARM Core Beam Test Plot Page 50 Test plots by Stephan Martens Diploma Thesis 2003

51 DCS Board Production Readiness Review Radiation Beamtest Plots : Voltage regulators MIC29301 Page 51 Tests by M. Stockmeier and D. Gottschalk * => 55 x 10 ALICE years

52 DCS Board Production Readiness Review Radiation Beamtest Plots : Voltage regulator LP3962 Page 52 Tests by M. Stockmeier and D. Gottschalk * => 107 x10 ALICE years

53 DCS Board Production Readiness Review Radiation Beamtest Plots : LP3962 recovery over night Page 53 Tests by M. Stockmeier and D. Gottschalk samples => 11 hours

54 DCS Board Production Readiness Review Radiation Beamtest Plots : ADC AD7708BRU Page 54 Tests by M. Stockmeier and D. Gottschalk * is equivalent to 90 x 10 ALICE years

55 DCS Board Production Readiness Review Radiation Beamtest : Others Page 55 CPLD Test : at 20pA in 2421s one error at 281s at 50 pA in 1079s one error at 49s at 100pA in 741s one error at 288s device dead after 126 x 10 ALICE years Tested with a twin shiftregister. Looking for nonequal values in both shifters and life activity of design. LVDS Receiver : at 20pA in 2021s no error at 50pA in 2835s no error LVDS Driver : at 20pA in 1799s no error equivalent to 37,5 x 10 ALICE years Tested with SCSN design in FPGA. Looking for data packet consistency. Tests by M. Stockmeier and D. Gottschalk

56 DCS Board Production Readiness Review Radiation Beamtest : Others Page 56 Optocoupler : 20pA 30min 2.5ms pulses no effect 50pA after 9min 12.5ms pulses dead 100pA after 15min 12.5ms pulses dead no pulse inversion occured Tested with rectangular pulses looking for erroneous puls inversions or dead. Ethernet Phy : 20pA >40min no errors equivalent to 50 x 10 ALICE years Tested with connection to a PC. Looking for lost or corrupted data packets. Ethernet driver Opamp : 20pA >40 min no errors equivalent to 50 x 10 ALICE years Tested with connection to a PC. Looking for lost or corrupted data packets. Tests by M. Stockmeier and D. Gottschalk

57 DCS Board Production Readiness Review Radiation Beamtest : Results Page 57 Results where quite encouraging. We found no „No go“. With some devices self-healing was observed. Mean time to failure is : 21 days for one DCS board

6. PHOS

59 Total Dose and Fluence in 10 ALICE years (ALICE-INT ) PHOS –Dose = 0.4 Gy –Flux (fast hadrons) = 63 hadrons/cm 2 s –Shielding of 18 cm lead tungstate is not taken into account

60 Irradiation plans FEE –APD + preamp (will go into beam August 31) –FEC (shaper + ALTRO) –TRU –TPC RCU –List of components that will be tested: 24LC256 MICROCHIP EEPROM GTL16612_TSSOP Philips GTL AD7417_TSSOP ANALOG DEVICES Temperature Sensor AD8039_SOIC ANALOG DEVICES OPAMP AD8544_SOIC ANALOG DEVICES OPAMP ALTRO-ST ST-Microelectronics ADC CY7C68013_TQFP128 CYPRESS USB EP1K _PQFP ALTERA FPGA EPC16 ALTERA FLASH KPC452 COSMO PHOTO COUPLER LM4041_1V2 NATIONAL REGULATOR LT1175_SOIC LINEAR REGULATOR MAX4454_TSSOP MAXIM-IC OPAMP MAX5308_TSSOP MAXIM-IC OPAMP MAX6033-A,5.0V MAXIM-IC REGULATOR MIC39151_TO263 MICREL REGULATOR MIC5239_SOIC-5.0 MICREL REGULATOR MIC5239_SOIC-ADJ MICREL REGULATOR MPC940L TQFP32_080 MOTOROLA REGULATOR OPA4364_TSSOP BURR-BROWN OPAMP 40MHZ, CFPT_125 C_MAC OSCILATOR TLC7733_SOIC Texas REGULATOR