Superscalars Lalitha Ramadoss Elec 6200 Computer Architetcure& Design Lectured by Dr.Vishwani Agrawal Electrical&computer Engineering Auburn.

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Instruction Level Parallelism and Superscalar Processors
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Presentation transcript:

superscalars Lalitha Ramadoss Elec 6200 Computer Architetcure& Design Lectured by Dr.Vishwani Agrawal Electrical&computer Engineering Auburn

What is a superscalar processor? Execute more than one instruction in each cycle Exploits Instruction level parallelism Motivation is Pipelining+Parallelism Better performance IBM RS/6000, TI SuperSPARC, the HP PA7100, and the DEC AXP 21064

Simple superscalar IFID INT FP MEMWB

Advanced Superscalars IF IF IF ID ID ID INT FP Lw/sw MEM MEM MEM WB WB WB

Instruction Level Parallelism Increasing the depth of pipeline to overlap more instructions-number of stages increased Replicating the internal components- multiple issue technique

Superscalar History Cray CDC Intel i960CA-1988,AMD-29000(1990)- RISC P6 PentiumPro and PentiumII,Intel CISC Power PC970

Superscalar concepts Scheduling Issues Execution Speculation WriteBack Retirement or Completion

Superscalar Classification Static Superscalars-execute instructions in program order Dynamic Superscalars-execute instructions out of order Dynamic with Speculation-ability to speculate on branches

Data Dependencies and Hazards Output Dependency MUL R1, R4, 15 ; R1 = R4 * 15 ADD R2, R1, 1 ; R2 = R1 + 1 MOVE R1, R3 ; R1 = R3 Antidependency ADD R1, R2, 1 ; R1 = R2 + 1 MOVE R2, R3 ; R2 = R3

Dynamic multiple issue processors Scheduling by Hardware l w $t0,20($s2) add $tl,$t0,$t2 sub $s4,$s4,$t3 Dynamic Pipeline scheduling

Dynamic scheduled Processors IF&ID RSRSRSRS IntInt FP FP Commit unit

References Computer Organization&Design Patterson Hennessy-2 & 3 edition ci/CompScience/csep/csep1.phy.ornl.gov/ca/node25.htmlhttp:// ci/CompScience/csep/csep1.phy.ornl.gov/ca/node25.html

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