System-level Trade-off of Networks-on-Chip Architecture Choices Network-on-Chip System-on-Chip Group, CSE-IMM, DTU

© System-on-Chip Group, CSE-IMM, DTU 2 Motivation abc 1 os 3 4 HdS mapping Application Middleware Hardware System-on-Chip Network Tasks and their dependencies ac Network b 2 5

© System-on-Chip Group, CSE-IMM, DTU 3 System-level Analysis Ω Consequences of different application decomposition and mappings of tasks to processors – software or hardware Ω Effects of different middleware – scheduling, synchronization and resource allocation policies Ω Effects of different network topologies and communication protocols.

© System-on-Chip Group, CSE-IMM, DTU 4 Outline Ω Motivation Ω Modeling of Communication  Properties of Networks-on-Chip (NoC) Ω Example Ω Design Space Exploration  Timing Aware and others Ω Conclusions

© System-on-Chip Group, CSE-IMM, DTU 5 Modeling of Communication ab a b ab BUS a b L1 R1 L2 R2 R3L4L3 ba 12 NoC R1 L1 R2 L2 R3 1 a b R1 L1 R2 L2 R3 2 Point-to-point Networks-on-Chip (eg. Mesh) BUS NoC combines multi-hop, concurrency and sharing

© System-on-Chip Group, CSE-IMM, DTU 6 System Analysis Methodology Choose hardware Map tasks Choose communication architecture Evaluate the performance and cost Iterate until performance and cost are met Optimal System!! Specifically for NoC

© System-on-Chip Group, CSE-IMM, DTU 7 Networked Multi-processors Ω Data transfers between processors are considered as message tasks Ω The network can be considered as a communication processor on which message tasks are scheduled Ω The network provides,  Topology = resource allocator  Protocol = scheduler

© System-on-Chip Group, CSE-IMM, DTU 8 Design Space Exploration z Tasks and their dependencies 2 x y bac Z Y X Network?? Allocation Aware bac Z YX Network?? Timing Aware Simple MPSoC Example 5 Identical Tasks 3 Inter-task Dependencies 3 Identical Processors Unknown Network!!

© System-on-Chip Group, CSE-IMM, DTU 9 Timing Aware bus b a c BUS x y z R1 R2 R3 L1L2 L3 L1 L2 b a c L x x 5 1 z y L1 L2 b a c L x y z z X: R1,L3,R3,L2,R2 Y: R3,L2,R2 Z: R1,L3,R3 z Tasks and their dependencies 2 x y PE a : 1 & 2 PE b : 3 PE c : 4 & 5 X: R1,L1,R2 Y: R3,L2,R2 Z: R1,L1,R2,L2,R3 X: BUS Y: BUS Z: BUS TORUSMESHBUS 888 L4 L1L2 L3 R3 R2R1 X: R1,L3,R3,L2,R2 Y: R3,L2,R2 Z: R1,L3,R3 X: R1,L3,R3,L2,R2 Y: R3,L2,R2 Z: R1,L3,R3

© System-on-Chip Group, CSE-IMM, DTU 10 Deadline-based Performance b a c bus x y z L1 L2 b a c L x y z z L1 L2 b a c L x x z y QoS Aware Any traffic from “a” has higher priority Timing Aware PE a : 1 & 2 PE b : 3 PE c : 4 &5 L3 L4 y x z b a c bus z y x L1 L2 b a c z L1 L3 b a c z x x xy Allocation Aware PE a : 2 & 3 PE b : 4 &5 PE c : 1 b a c bus x y z L1 L2 b a c L x x z y L1 L2 b a c L x y z z TORUSMESHBUS

© System-on-Chip Group, CSE-IMM, DTU 11 Power Profile Timing Aware PE a : 1 & 2 PE b : 3 PE c : 4 &5 L4 b a c bus z y x L3 b a c z L1 L2 b a c zx xy Allocation Aware PE a : 2 & 3 PE b : 4 &5 PE c : 1 b a c bus x y z L1 L2 b a c L x x z y QoS Aware Any traffic from “a” has higher priority b a c bus x y z L1 L2 b a c L x x z y L2 b a c L3 TORUS L1 L2 b a c L x y z z y x L z x x y z z MESHBUS Deadline- based Performance

© System-on-Chip Group, CSE-IMM, DTU 12 Power Profile L3 L1 L2 b a c z zx xy b a c bus x y z TORUSBUS Deadline- based Performance = 100 power unit = 10 power unit Power Profile power units power-units/cycle power-units/cycle

© System-on-Chip Group, CSE-IMM, DTU 13 Power Profile over 3 Period Torus Bus ~4 cycles faster Torus is faster but causes power spikes!!! 250% 201%

© System-on-Chip Group, CSE-IMM, DTU 14 Conclusions Ω System-level modeling framework which combines application, middleware and execution platform Ω Extension to model network-on-chip Ω Example  System-level trade-off analysis  Early design space exploration Ω Work in progress  Find real application for evaluation!!