A scheme to overcome data hazards Dynamic Scheduling A scheme to overcome data hazards

Advantages of Dynamic Scheduling Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior It handles cases when dependences unknown at compile time it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve It allows code that compiled for one pipeline to run efficiently on a different pipeline It simplifies the compiler Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling

HW Schemes: Instruction Parallelism Key idea: Allow instructions behind stall to proceed DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F12,F8,F14 Enables out-of-order execution and allows out-of-order completion (e.g., SUBD) In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder

Dynamic Scheduling Step 1 Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue Split the ID pipe stage of simple 5-stage pipeline into 2 stages: Issue—Decode instructions, check for structural hazards Read operands—Wait until no data hazards, then read operands

Tomasulo Algorithm Control & buffers distributed with Function Units (FU) FU buffers called “reservation stations”; have pending operands Registers in instructions replaced by values or pointers to reservation stations(RS); called register renaming; Avoids: WAR WAW hazards More reservation stations than registers, so can do optimizations compilers cannot Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs Load and Stores treated as FUs with RSs as well. Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue. RX inst. i RX  inst. j

Tomasulo scheme FP Multipliers FP adders From memory From instruction unit 6 5 4 3 2 1 FP Registers FP Operation queue Load buffers Operand buses 3 2 1 Store buffers Operation bus To memory 3 2 1 2 1 Reservation Stations FP Multipliers FP adders Common data bus (CDB)

Reservation Station Components Op—Operation to perform in the unit (e.g., + or –) Vj, Vk—Value of Source operands Store buffers has V field, result to be stored Qj, Qk—Reservation stations producing source registers (value to be written) Note: No ready flags as in Scoreboard; Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy—Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. What you might have thought 1. 4 stages of instruction executino 2.Status of FU: Normal things to keep track of (RAW & structura for busyl): Fi from instruction format of the mahine (Fi is dest) Add unit can Add or Sub Rj, Rk - status of registers (Yes means ready) Qj,Qk - If a no in Rj, Rk, means waiting for a FU to write result; Qj, Qk means wihch FU waiting for it 3.Status of register result (WAW &WAR)s: which FU is going to write into registers Scoreboard on 6600 = size of FU 6.7, 6.8, 6.9, 6.12, 6.13, 6.16, 6.17 FU latencies: Add 2, Mult 10, Div 40 clocks

Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (“go to” bus) Common data bus: data + source (“come from” bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast

Tomasulo Example Cycle 0

FP Multipliers FP adders Cycle: 0 From memory From instruction unit FP Registers 6 5 4 3 2 1 Load buffers FP operation queue Store buffers Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 1 From memory From instruction unit FP Registers 6 5 4 3 2 1 34+R2 F6 : load1 Load buffers FP operation queue Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 2 From memory From instruction unit FP Registers 6 5 4 3 2 45+R3 1 34+R2 F2 : load2 F6 : load1 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 3 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 45+R3 1 Mem[34+R2] F2 : load2 F6 : load1 SUB F8,F6,F2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 M load2 “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 4 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 Mem[45+R3] 1 F2 : load2 DIVD F10,F0,F6 F6 Mem[34+R2] F6 : load1 SUB F8,F6,F2 F8: add1 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) L1: Mem[34+R2] Operation bus To memory L1: Mem[34+R2] L1: Mem[34+R2] 3 2 1 S load1 load2 Reservation Stations 2 M load2 “F4” 1 Mem[34+R2] FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP Multipliers FP adders FP adders Cycle: 5 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F2  Mem[45+R3] F2 : load2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers L2: Mem[45+R3] LD F2, 45(R3) Operand buses 3 2 1 Operation bus To memory L2: Mem[45+R3] L2: Mem[45+R3] 3 2 1 S Mem[R2] load2 Reservation Stations D Mult1 2 M load2 “F4” 1 Mem[45+R3] Mem[45+R3] Mem[45+R3] FP Multipliers FP Multipliers FP adders FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 6 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 7 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 8 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8  M()-M() F8: add1 SUB F8,F6,F2 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 M()-M() FP Multipliers FP adders Common data bus (CDB) Add1: M()-M()

FP Multipliers FP adders Cycle: 9 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 10 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 11 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 F6  (M()-m())+M() DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB) Add2: (M()-M())+M()

FP Multipliers FP adders Cycle: 12 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 13 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 14 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 15 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 16 From memory From instruction unit FP Registers F0  M()*F4 F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 M()*F4 FP Multipliers FP adders Common data bus (CDB) Mult1: M()*F4

FP Multipliers FP adders Cycle: 17 From memory From instruction unit FP Registers 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 Load buffers FP operation queue Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D M()*F4 M[R3] 2 1 FP Multipliers FP adders Common data bus (CDB)

FP Multipliers FP adders Cycle: 57 From memory From instruction unit FP Registers 6 5 4 3 2 1 DIVD F10,F0,F6 F10  M()*F4 / M() F10: mult2 Load buffers FP operation queue Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D M()*F4 M[R3] 2 1 FP Multipliers FP adders Common data bus (CDB) Mult2: M()*F4 / M()

Tomasulo Example Cycle 1 Yes

Tomasulo Example Cycle 2 Note: Unlike 6600, can have multiple loads outstanding

Tomasulo Example Cycle 3 Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued vs. scoreboard Load1 completing; what is waiting for Load1?

Tomasulo Example Cycle 4 Load2 completing; what is waiting for it?

Tomasulo Example Cycle 5

Tomasulo Example Cycle 6 Issue ADDD here vs. scoreboard?

Tomasulo Example Cycle 7 Add1 completing; what is waiting for it?

Tomasulo Example Cycle 8

Tomasulo Example Cycle 9

Tomasulo Example Cycle 10 Add2 completing; what is waiting for it?

Tomasulo Example Cycle 11 Write result of ADDD here vs. scoreboard?

Tomasulo Example Cycle 12 Note: all quick instructions complete already

Tomasulo Example Cycle 13

Tomasulo Example Cycle 14

Tomasulo Example Cycle 15 Mult1 completing; what is waiting for it?

Tomasulo Example Cycle 16 Note: Just waiting for divide

Tomasulo Example Cycle 55

Tomasulo Example Cycle 56 Mult 2 completing; what is waiting for it?

Tomasulo Example Cycle 57 Again, in-order issue, out-of-order execution, completion

Tomasulo Drawbacks Complexity delays of 360/91, MIPS 10000, IBM 620? Many associative stores (CDB) at high speed Performance limited by Common Data Bus Multiple CDBs => more FU logic for parallel assoc stores

Tomasulo Loop Example Loop: LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop Assume Multiply takes 4 clocks Assume first load takes 8 clocks (cache miss?), second load takes 4 clocks (hit) To be clear, will show clocks for SUBI, BNEZ Reality, integer instructions ahead

Loop Example Cycle 0

Loop Example Cycle 1

Loop Example Cycle 2

Loop Example Cycle 3 Note: MULT1 has no registers names in RS

Loop Example Cycle 4

Loop Example Cycle 5

Loop Example Cycle 6 Note: F0 never sees Load1 result

Loop Example Cycle 7 Note: MULT2 has no registers names in RS

Loop Example Cycle 8

Loop Example Cycle 9 Load1 completing; what is waiting for it?

Loop Example Cycle 10 Load2 completing; what is waiting for it?

Loop Example Cycle 11

Loop Example Cycle 12

Loop Example Cycle 13

Loop Example Cycle 14 Mult1 completing; what is waiting for it?

Loop Example Cycle 15 Mult2 completing; what is waiting for it?

Loop Example Cycle 16

Loop Example Cycle 17

Loop Example Cycle 18

Loop Example Cycle 19

Loop Example Cycle 20

Loop Example Cycle 21

Tomasulo Summary Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards of Scoreboard Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Pentium II; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264

Reorder buffer information Branch correction Reorder buffer information Fetch Unit Dispatch unit w/ 8-entry instruction queue Completion unit w/ reorder buffer Instruction dispatch buses Instruction Cache Register nos. Register nos. Register nos. Instruction Operation buses Register nos. GP operand buses FP operand buses Reservation Stations XSU0 XSU1 BPU MCFXU LSU FPU GP result buses FP result buses Result status buses Data Cache