RISC / CISC Architecture By: Ramtin Raji Kermani Ramtin Raji Kermani Rayan Arasteh Rayan Arasteh An Introduction to Professor: Mr. Khayami Mr. Khayami Computer Architectures Computer Architectures RISC / CISC Characteristics RISC / CISC Characteristics RISC / CISC Cons & Pros RISC / CISC Cons & Pros Comparing RISC & CISC Comparing RISC & CISC Summery Summery

Computer Architecture covers three aspects of computer design: RISC / CISC Architecture Instruction Set Architecture (ISA) Instruction Set Architecture (ISA) Computer Organization Computer Organization Computer Hardware Computer Hardware

RISC / CISC Architecture Computer OrganizationComputer Organization Includes high level aspects of a design, such as Memory system, Bus Architecture, Design of internal CPU & … Computer HardwareComputer Hardware Refers to the specifics of a machine Included the detailed Logic Design & the packaging technology at the machine. Instruction Set Architecture (ISA) Instruction Set Architecture (ISA) Refers to the actual programming visible machine interface such as instruction set, registers, memory organizations.

Instruction Set Architecture (ISA) What's an Instruction Set ? What's an Instruction Set ? 1.Set of all instructions understood by the CPU 2.Each instruction directly executed in hardware Instruction Set Representation Instruction Set Representation 1.Sequence of bits, typically 1-4 words 2.May be variable length of fixed length 3.Some bits represent the opcode, the others represent the operand.

Instruction Set Architecture : (ISA) Instruction Set Affects CPU Performance - Exec time = Instruction_Count * CPI * Cycle_Time Instruction Set Source Code Compiler Object Code Inst. Exec. Inst. Decode Inst. Fetch Instruction Count CPI & Cycle Time

Classes of Instruction Set Architectures: 1. Stack Based: Implicitly use the top of a stack PUSH X, PUSH Y, ADD, POP Z Z = X + Y 2. Accumulator Based: Implicitly use an Accumulator LOAD X, ADD Y, STORE Z 3. GPR – General purpose Registers Operands are explicit and may be in memory or register LOAD R1, X LOAD R1, X LOAD R2, YOR ADD R1, Y ADD R1, R2, R3 STORE R1, Z STORE R3, Z

Classes of Instruction Set Architectures: Comments: Stack Based: Short, Complex programming, Stack overhead Accumulator: Problem of having different data types GPR: Most commonly used today, larg number of registers, Let compiler Do the job! Two main approaches of ISA Two main approaches of ISA: RISC: Reduced Instruction Set Computer CISC: Complex Instruction Set Computer

Complex Instruction Set Computer. Some instances: IBM 360 (also 370), Mainframes, DEC VAX, Intel x86, Motorola 680x0 IBM 360 (also 370), Mainframes, DEC VAX, Intel x86, Motorola 680x0. Why it developed?. At that time, compiler technology was not powerful enough, So most of the Job was done by Hardware.. At that time, compiler technology was not powerful enough, So most of the Job was done by Hardware.. Memories were small, so high data density was something to notice.. Memories were small, so high data density was something to notice.. Need for more sophisticated instructions to reduce software problems.. Need for more sophisticated instructions to reduce software problems.. Greater variety of instructions would simplify compilers.. Greater variety of instructions would simplify compilers.. Decreasing the gap between the High level languages and Assembly language.. Decreasing the gap between the High level languages and Assembly language.

RISC / CISC Architecture CISC Characteristics:. Several hundred (complex) instructions (highly encoded). Array operation, BCD, Procedure calls, Case statements. Large number of addressing modes (usually 5-20 ways). Many number of data types. Long, complex and slow microprogram. Each instruction takes several clock cycles to execute. Variable size instruction format. Included high level functions of high level languages. High instruction density. Microprogrammed Control Unit. Simplifying compiler programming

RISC / CISC Architecture Reduced Instruction Set Computer. Some instances: SPARC, MIPS, DLX. Why it developed?. Compilers are good; let them do the hard work. Very simple and small instruction set is faster. Instructions are simple enough to be executed directly in HW. Decoding of instructions of the same size is easier. Possibility to have advanced processing options. Pipelining. Parallel Processing

RISC / CISC Architecture RISC Characteristics:. A few instructions. A few addressing modes. Memory access is restricted to LOAD & STROE instructions. All Operation is done in CPU. Fixed length instructions  easy decoding. Each instruction executes in one clock cycle. Hardware control unit, instead of Microprogrammed control. Usually Register-Register operations. High speed execution time. Uses overlapped registers to decrease data transfer time

RISC / CISC Architecture Ctrl Unit Cache Micro Programmed Ctrl Unit Inst. & Data Path Main Mem HW Ctrl Unit Data Cache Instruction Cache Data Path Inst Data Main Memory CISC Architecture with UCtrl Unit & Unified Cache RISC with Hardwired Ctrl Unit And Split Cache

RISC / CISC Architecture Thanks for your attention … Ramtin Raji Kermani Rayan Arasteh Winter 2005