IN2305-II Embedded Programming Lecture 2: Digital Logic

in2305-II: L22 Main Subjects Combinational logic: no memory (state) Sequential logic: state (clocked) VHDL implementation issues How to model / synthesize digital circuits

in2305-II: L23 VHDL in a Nutshell y <= x or c; c <= a and b; z <= y when p else not y when not p; process (s) begin a <= not s; end process; -- a <= not s; concurrent execution model: everything executes in parallel (data flow) behavioral versus structural specification: structural = composition (“wiring”) sequential behavior (state): z latch process (clk) begin y latch if clk = ‘1’ then q <= d; -- d-ff (pos edge-trig) end process; note: within process: sequential execution model

in2305-II: L24 Combinational Logic y <= a and b; a b y a b y ay y <= a or b; y <= not a; Essence of combinatorics: process triggered by the input events (y assignment is synchronous with a and b signal changes)

in2305-II: L25 Example Combinational Blocks with a select -- enc y <= “00” when “0001”, “01” when “0010”, “10” when “0100”, “11” when “1000”; a d y dec 2 4 ay enc 42 with a select -- dec z <= “0001” when “00”, “0010” when “01”, “0100” when “10”, “1000” when “11”; y <= z when d = ‘1’ else “0000”;

in2305-II: L26 Example Combinational Blocks a b y mux with s select -- mux y <= a when ‘0’, b when ‘1’; s a b 8 8 op 8 y with op select -- alu y <= a + b when ‘00’, a and b when ‘01’,...

in2305-II: L27 Sequential Logic process (clk) -- d-ff begin if rising_edge(clk) then q <= d; end if; end process; d Essence of state: assignment is NOT triggered by input events but by an auxiliary signal (usually called a clock) q clk process (d) -- buffer begin q combinational! end process; dff

in2305-II: L28 Comb. + Sequential: FSM process -- fsm begin wait until rising_edge(clk); case s is when 0x”00” => if (x = ‘1’) then s <= 0x”01”; end if; y <= ‘1’; when 0x”01” =>.. end case; end process; s clk dff cmb Mealy FSM: y = f( s, x ) Moore FSM: y = f( s ) xy

in2305-II: L29 Example Sequential Blocks (1) y ram process -- ram begin wait until rising_edge(clk); if (we = ‘1’) then mem(a) <= d; end if; y <= mem(a); end process; clk d a we

in2305-II: L210 Example Sequential Blocks (2) y ctr process -- counter begin wait until rising_edge(clk); if (rst = ‘1’) then c ‘0’); else c <= c + 1; end if; y <= c; end process; clk rst

in2305-II: L211 Tri-state Logic: Busses a y oe_a b oe_b y <= a when oe_a = ‘1’ else ‘Z’; y <= b when oe_b = ‘1’ else ‘Z’; More efficient than mux for n-bit data paths dec

in2305-II: L212 Simple Processor (Delta) r0r1 pc alu.. decrom a rn... data bus

in2305-II: L213 VHDL Implementation Issues Structural synthesis entities reg, tristate-buf, rom, enc, alu, connected by bus each entity behavioral example: Delta-1 source code Behavioral synthesis entities cpu, rom cpu entirely behavioral example: X32 source code pro: simple, understandable code, virtually no HW design con: more burden on synthesizer, less efficient HW (space), potentially larger critical path which may lead to slower freq. Trade-off depends on appl. and available resources

in2305-II: L214 Behavioral Approach process -- delta cpu (behavioral) begin wait until rising_edge(clk);.. case op is when.. => pc <= op(..); -- jp.. when.. => r(a) <= acc; -- st r.. when.. => acc <= acc + op(..); -- add #.. when.. => acc <= acc and r(a); -- and r.. when.. => if (zero = ‘1’) then -- bz.. pc <= op(..); end if; end case; if (-- not jp/bz/bc/..) then pc <= pc + 1; end process;

in2305-II: L215 Button Debouncer V cc GND x:x y: time x’ 10 x 2 t’ t,x t,x’ x x’ 0: output’, timer enable’ 1: output, timer enable 2: output, timer enable’ tmret clk

in2305-II: L216 Debouncer Code (1) process -- fsm (behavioral) begin wait until rising_edge(clk); case s is when “00” => if (x = ‘1’) then s <= ”01”; end if; when ”01” => if (t = ‘1’) then s <= “00” when (x = ‘0’) else “10” when (x = ‘1’); end if; when “10” => if (x = ‘0’) then s <= “00”; end if; end case; output <= ‘0’ when (s = “00”) else ‘1’; timer_enable <= ‘1’ when (s = “01”) else ‘0’; end process;

in2305-II: L217 Debouncer Code (2) process -- timer (behavioral) begin wait until rising_edge(clk); if (timer_enable = ‘0’) then counter ‘0’); t <= ‘0’; else if (counter < THRESHOLD) then counter <= counter + 1; else t <= ‘1’; end if; end process;

in2305-II: L218 Demo using FPGA board FPGAs are a flexible, low-cost “bread-board” to experiment with HW using SW (VHDL) instead of ICs and wires Xilinx Board: Cheap: $99

in2305-II: L219 Demo Demo.. (vhdl_projects.tgz, debouncer)

in2305-II: L220 Autorepeat input: output: time i’ /o/o’ i t1’.i t1.it2.i t2’.i i’ t1t2 t2’.i t2.i /o i’ t2 i’ clk t2

in2305-II: L221 Autorepeat Code process -- fsm, using counter is more simple begin wait until rising_edge(clk); case s is when “00” => if i = ‘1’ then c <=..; s <= ”01”; end if; when ”01” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c >.. then c <=..; s <= “10”; end if; when “10” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c >.. then c <=..; s <= “11”; end if; when “11” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c >.. then c <=..; s <= “10”; end if; end case; output <= ‘1’ when s = “01” and s = “11” else ‘0’; end process;

in2305-II: L222 Demo Demo.. (vhdl_projects.tgz, reaction timer)