cs 152 L1 Intro.1 Patterson Fall 97 ©UCB ECE 366 Computer Architecture Lecture 3 Shantanu Dutt ( Decomposition of Computer Organization & Generic Instruction Processing Note: These slides have been solely prepared by Shantanu Dutt. The “Patterson Fall 97 copyright UCB” logo appearing on the bottom right corner is incorrect (as is the logo on the bottom-left corner). They appear because the same template as Dave Patterson’s intro slides used in Lect. 1-2 were used for these slides by mistake. The incorrect logos will be removed later (haven’t yet figured out how to).

cs 152 L1 Intro.2 Patterson Fall 97 ©UCB Overview °Decomposition of a Computer °Basic Functions of a Control Unit -- Read and Write Selects °Generic Instruction Processing in the Control and Datapaths

cs 152 L1 Intro.3 Patterson Fall 97 ©UCB Decomposition of a Computer’s Organization (Hardware) Computer = Processor + Memory + I/O + Interfaces Processor Connections (High/Low-Speed) + Interfaces I/O Devices (Disks, N/W conn., Monitor, Keybd, Prntr) Memory

cs 152 L1 Intro.4 Patterson Fall 97 ©UCB Decomposition of a Computer’s Organization (Hardware) Processor = Datapath + Control Note: The Datapath includes the top levels of the memory hierarchy (e.g., 1st level caches). Some include the entire memory hierarchy as part of the datapath. Datapath (Processing of data according to instructions)) Control Unit (Orchestrates the correct sequence of micro-instructions or micro-stages in the processing of instrs.) Control Signals Status Signals

cs 152 L1 Intro.5 Patterson Fall 97 ©UCB Decomposition of a Computer’s Organization (Hardware) Datapath = (Data Mem?) + Register File + ALU Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg.

cs 152 L1 Intro.6 Patterson Fall 97 ©UCB Decomposition of a Computer’s Organization (Hardware) Control = (Instr. Mem?) + PC + Instr. Reg. + C.U. (FSM) Instruction Memory Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Status Control Datapath

cs 152 L1 Intro.7 Patterson Fall 97 ©UCB Basic Functions of the C.U. °The CU functions by sending signals in each state that do the following: Read Selection = Connection to a bus from various sources (e.g., buses, registers, FU o/ps) using Muxes or Tri-State Buffers (+ Decoders). Only one source can be read onto a bus. Write Selection = Loading one or more registers w/ the data at the input of the registers. °Read occurs at the beginning of a clock cycle (cc) and the corresponding write into the target register occurs at the rising edge of the next cc (assuming Read finishes by that time; in general the Write occurs at the rising edge of the next cc after the Read finishes). Control signals for both need to be valid in the current cc r1 2:1 Mux rbrcrdra Bus r2 sel=0 ldra=0ldrb=1ldrc=0ldrd=0 01 Write/Load Read Period sel=0, ldrb=1

cs 152 L1 Intro.8 Patterson Fall 97 ©UCB Basic Functions of the C.U. °The C.U. orchestrates the processing of instructions along a datapath by a simple sequence of Read and Write selects in each cc °A Register-Transfer-Like Notation: Read Operation: r2 => Bus (r2 o/p connected to the bus) Write Operation: rb <= Bus; rd <= Bus (Bus value written/loaded to registers rb, rd Note final effect of the above Read and Write in the same cc (I.e. Read and Write select control signals valid in the same cc) is : rb <= r2; rd <= r2 r1 2:1 Mux rbrcrdra Bus r2 sel=1 ldra=0ldrb=1ldrc=0ldrd=0 01 Write/Load Read Period sel=1, ldrb=1, ldrd=1

cs 152 L1 Intro.9 Patterson Fall 97 ©UCB Instruction Processing: Phase 1 -- Fetch Instruction: ADD r2 r3 r7 [r2 <- r3 + r7] Memory Interface (Addr. + Data Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. 1 1 Instruction Memory Connect PC to Addr. Bus & Read Mem. Onto Data Bus Load IR when Instr. Avail [IR <= Data Bus] Status signals Source & dest reg addr [PC=>Addr Bus; Mem[PC] => Data Bus]

cs 152 L1 Intro.10 Patterson Fall 97 ©UCB Instruction Processing: Phase 2 -- Decode & Incr. PC Instruction: ADD r2 r3 r7 [r2 <- r3 + r7] Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. 2 Instruction Memory 2 Start State for ADD Decode State Load PC w/ o/p of Update H/W [PC <= PC Upd o/p]

cs 152 L1 Intro.11 Patterson Fall 97 ©UCB Instruction Processing: Phase 3 --Read Operands in RF Instruction: ADD r2 r3 r7 [r2 <- r3 + r7] Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. Instruction Memory 3 r3 r7 Connect regs specified by source fields of IR to Buses A and B [r3 => BusA; r7=> BusB] 3 Load appr. internal regs of ALU w/ Bus A, B data [rega <= Bus A; regb<= BusB

cs 152 L1 Intro.12 Patterson Fall 97 ©UCB Instruction Processing: Phase 4 --Execute (in ALU) Instruction: ADD r2 r3 r7 [r2 <- r3 + r7] Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. Instruction Memory 4 4 Select ADD FU to connect to ALU o/p reg [ADD o/p => ALU o/p] Load o/p reg w/ ALU o/p [o/p reg <= ALU o/p] ADD

cs 152 L1 Intro.13 Patterson Fall 97 ©UCB Instruction Processing: Phase 5 --Write Back (to RF) Instruction: ADD r2 r3 r7 [r2 <- r3 + r7] Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. Instruction Memory 5 Write data on write port to reg specified in dest filed of IR [r2 <= o/p reg] r2