Alice EMCAL meeting, July EMCAL jet trigger status Olivier BOURRION LPSC, Grenoble

Alice EMCAL meeting, July Trigger specification : L0 trigger : OR of the 34 L0 calculated by the TRU. L1-gamma trigger: Energy summed over sliding window of 4x4 towers (2x2 fast OR) and compared to a multiplicity corrected threshold. L1-jet trigger : Energy summed over a sliding window of n*n subregions and compared to a multiplicity corrected threshold (a subregion is defined as 8x8 towers)‏ Reminder : the Summary Trigger Unit STU TRU L0 L1-gamma L1-jet 34 TRU Multiplicity from V0 4 diff pair Ethernet CAT7 cable TRU is clocked by the BC clock forwarded by STU (40.08MHz)‏ TTC link To CTP DDL DCS Put trigger data in the data stream on L2a (via DDL)‏ LVDS links

Alice EMCAL meeting, July Detector layout as understood

Alice EMCAL meeting, July EMCAL layout (1/2)‏ Region orientation / numbering? View from beam or cal frame? Mirrored SM The understanding of the layout is the key point for building the trigger algorithm

Alice EMCAL meeting, July EMCAL layout for one TRU (2/2)‏ The ADC channel number has to be known by STU, in order to compute the triggers For instance, one 4X4 window is channel 5,6,9 and 10 Confirmation of the ADC channel affectation vs geometrical position ?

Alice EMCAL meeting, July Functional simulation scenario (see R. GUERNANE talk) Overlapping 2 neighboring regions in phi 2.Overlapping 2 neighboring regions in Z 3.Overlapping 4 regions

Alice EMCAL meeting, July Current status

Alice EMCAL meeting, July DCS board modification and testing The transformer less Ethernet board was tested at LCMI in march 2008 No packet 0.53 T

Alice EMCAL meeting, July Thermal study results (work done by Julien GIRAUD : Problem: board will dissipate nearly 36 W Assumptions: –water flow 20°C, tube  =5 mm, Q= 1l/min –Hot component coupled with a 2 mm copper plate via a thermal foam hottest spot 36°C (conservative, convection neglected) 2 mm copper plate

Alice EMCAL meeting, July Actual STU board layout For TRU: Dual stacked RJ on left side, 20 on front, 10 on right side

Alice EMCAL meeting, July Summary of the STU status Work done so far –LVDS Link validation (july 07) –DCS hardware modification and qualification –Thermal study –PVSS and DCS know-how gained by G. DARGAUD on Pixel trigger –Some VHDL available (deserializer, TTCrq interface)‏ –Board layout, fabrication in progress (board received july 11th) To do –VHDL design: final VHDL degraded versions for tests (TRU link only, limited L1-gamma, L1-jet). This has to be defined –TRU link validation (to be discussed)‏ –Interfaces tests and validation (DDL, V0, TTC)‏ –PVSS driver for Emcal

Alice EMCAL meeting, July Proposed TRU-STU link validation methodology 1.An emitting buffer is loaded via the testing tools 2.A frame transfer is initiated 3.The receiving buffer is read by the testing tools Above steps have to be repeated many times with different packet contents. This scheme will exercise the link as in the final design. -This is somewhat similar to the tests performed in july 2007 on the TOR board -Has to be performed before TRU full production order (September 08??) TRU USB  LVDS USB Slow control LVDS CAT7 LVDS cable 15m Testing tools STU

Alice EMCAL meeting, July SPARES

Alice EMCAL meeting, July Available L1 processing time t interaction One or several TRU sends L0 to STU 0 ns 600 ns STU forward one L0 to CTP 700 ns L0 from CTP at RCU 1200 ns L1 reception deadline (at CTP input)‏ TRU start of transmission 1400 ns All data in STU 3155 ns 6100 ns PHOS: 112*12 bit/800Mbs+75ns=1.755µs EMCAL: 96*12 bit/800Mbs+75ns=1.515µs 75ns : estimated 15m of wire L1 emission deadline (at STU ouput)‏ 5900 ns 200ns : estimated 40m of wirePHOS: 112*12 bit/800Mbs+75ns=1.755µs EMCAL: 96*12 bit/800Mbs+75ns=1.515µs 75ns : estimated 15m of wire Available 2745 ns (PHOS)‏ Available 2985 ns (EMCAL)‏

Alice EMCAL meeting, July L1-gamma processing (1/2)‏ Now the numbers are the readout order Column are read top to bottom and then row right to left Refering to the previous slide DPRAM readout is 4,3,1,2,8,7,5,6,… A region A+1,R+1 region R region

Alice EMCAL meeting, July L1-gamma processing (2/2)‏ The trigger is computed for each region, with neighboring region inputs. Requires 4 accumulators (col size) X 2 (window size)‏ Latency is roughly 100 X 1/120MHz~900 ns

Alice EMCAL meeting, July L1-jet processing (1/2)‏ Based on P. Jacobs proposal: 6 subregions are created in each region. Numbers are the readout order and not the ADC channel number Total: 204 subregions Below subregion delimitation, 4x4 fast OR  8x8=64 towers Each subregion energy sum is computed in parallel with L1-gamma 6 accumulators (no overlapping)  latency ~900 ns

Alice EMCAL meeting, July L1-jet processing (2/2)‏ The algorithm to apply is somewhat similar to L1-gamma except that here the columns contains 12 elements  No accumulators for 1 subregion patch, direct threshold comparison 12*2 accumulators for a 2X2 subregion patch 12*3 accumulators for 3X3 subregion patch Latency: >204 clock cycles  >1.7µs (remaining margin: =385ns)‏