RTL Design Introduction Decoder Encoder Multiplexer Tri-state Buffer Look up Table

INTRODUCTION So far all we have shown was based on gate level design. When considering functionality of elements as a base of our design, a gate level design isn’t meaningful enough. We will concentrate on functional packages from now on. This level of design referred to as RTL (Register Transfer Level) design and the components which are called RTL components are divided into combinational and sequential types RTL level component Definition Structure Cascading Configuration Verilog Application All of this certainly doesn’t mean our need for gates and transistors has been eliminated, especially when matching is needed between RTL components (glue logic)

Decoder We’ll introduce this package by examining a binary decoder 𝑦 0 1 1 𝑦 1 𝑦 0 , 𝑦 1 , 𝑦 2 & 𝑦 3 will be activated when the inputs are 00,01,10 &11 𝑦 2 𝑦 3

Decoder( cont. ) Such a package still isn’t general as such and needs to have the ability of cascading, for the user to be able to construct larger decoders through combining smaller ones. Adding an extra input for enabling/disabling the output will help us in this arena as we will show later on Problems can occur in such a design. Firstly we have used and gates (constructed of nand + inverter in CMOS) when we don’t know whether or not the user of our package really needs active-high outputs. We have also, for the same reason, used a lot of pull ups and pull downs and an excessive use of transistors The decoder shown in the last slide is known as a 2-to-4 decoder and a simple structure for it can be the following circuit To resolve the mentioned problems, we change the And gates to Nand gates and so our truth table will be changed module dcd2to4(input l0,l1,en,output [3:0]y); assign y=(en==1'b0)?4'b1111: ({l0,l1}==2'b00)?4'b1110: ({l0,l1}==2'b01)?4'b1101: ({l0,l1}==2'b10)?4'b1011: ({l0,l1}==2'b11)?4'b0111:4'b1111; endmodule en 𝒍 𝟏 𝒍 𝟎 𝒚 𝟎 𝒚 𝟏 𝒚 𝟐 𝒚 𝟑 1 - en 𝒍 𝟏 𝒍 𝟎 𝒚 𝟎 𝒚 𝟏 𝒚 𝟐 𝒚 𝟑 1 -

Decoder ( cont. ) Looking at our design so far may cause some new questions. For instance have we told our user that any signal feeds to the EN input has been used to drive 4 gates? Have we not misled the user by not using a standard method? There can be two possible ways to resolve this To document the number of gates a particular input is used to drive A preferable solution is to construct our structure by a convention that no input is used to drive more than one gate. To do this, we need to buffer the EN input through an inverter that will change these inputs’ activity level to low. The same can be done for inputs ‘a’ and ‘b’ without changing their activity level, as shown in the following figure

Decoder ( cont. ) We’ll show this fact by constructing a 3-to-8 and a 4-to-16 decoder using 2-to-4 decoders We will now show how adding the EN input has given our package the ability of cascading.

Decoder ( cont. ) Decoders can be used to realize switching functions. To do this we will need to OR outputs (relative to the corresponding minterms) of our decoder with an active-low inputs or gate Example

Error will happen when the number is not between 0 and 9 Decoder ( cont. ) Example(Seven Segment DCD) 𝐼 0 𝐼 1 𝐼 2 𝐼 3 a b c d e f g en g a d e c f b 1 2 3 4 9 8 7 6 5 error Error will happen when the number is not between 0 and 9

Encoder We talked about using a decoder to decode a coded number, obviously there has to also be a way of encoding data as well. 1 1

Encoder ( cont. ) An encoder can find so many uses. For instance consider a stage in a CPU’s working time when two interrupts are sent to it at the same time. One asking for the process of a key press event and the other pointing to a power failure. Obviously in such a situation the first need not be processed because the second interrupt indicates a very severe problem (specially in OSs like Linux). There does actually occur a time when two or more of the inputs are active, we will be using a priority encoder. In such a case the input line with the higher number is chosen to be of higher priority. This means that for instance if we choose X3 as a power failure interrupt line, no other interrupt request will ever surpass it through priority.