ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 09/05/2007

Master / Slave Structure TCLK SLOT A (n) SWITCHES MASTER/SLAVE CARD_PRESENT TCLK_PRESENT TRIGGER CLOCK SYNCs And DATA MANAGERS SLOT B (n+1) MASTER/SLAVE CARD_PRESENT TCLK_PRESENT TRIGGER CLOCK SYNCs And DATA MANAGERS DATAPATH CLOCK AND SYNCS DATAPATH CLOCK AND SYNCS

200Mhz Clock and Clock SYNC distribution TCLK GTS CORE SEGMENT PLL SWITCH GTS_CLOCK VIRTEX4 FX100 MAIN FPGA SMB INSP VIRTEX4 LX25 DATA DISTRIBUTON MGT CLOCK SYSTEM CLOCK_ SYNC 200MHz FANOUT SWITCH MASTER 100MHz SWITCH SEGMENT PLL SWITCH GTS_CLOCK VIRTEX4 FX100 MAIN FPGA SMB INSP VIRTEX4 LX25 DATA DISTRIBUTON MGT CLOCK SYSTEM CLOCK_ SYNC 200MHz FANOUT SWITCH SLAVE 100MHz SWITCH PPC_CLOCK 100MHz 200MHz 100MHz 200MHz $07 – D0 $07 – D1 $07 – D2 $08 – D1 $07 – D0 $07 – D1 $07 – D2 $08 – D1 PPC_CLOCK

GTS ADCs CLOCK SYNC distribution TCLK GTS CORE SEGMENT FANOUT SYNC_RTN MASTER SLAVE SEGMENT FANOUT GTS_SYNC 100MHz clock with missed periods as SYNC event SWITCH SYNC_AUX SYNC_RTN SYNC_AUX

Serializers SYNC signal distribution TCLK GTS CORE SEGMENT FANOUT MASTER SLAVE SEGMENT TRIGGER FPGA MAIN FPGA SWITCH SEGMENT FANOUT TRIGGER FPGA MAIN FPGA SWITCH 10MHz clock signal (the patterns must be equal at any rising edge)

Bcast & Msg Handler Serialized SERIALIZERS 8  1 8 FROM REMOTE (TCLK) GTS MEZZANINE MAIN FPGA Msg_str0 Msg_str1 B_cast_data (7 downto 0) B_cast_str0 B_cast_str1 LLP Status (7 downto 0) GTS Status (7 downto 0) Msg_data (7 downto 0) SEG/CORE MEZZANINE Msg_str0 Msg_str1 LLP Status (7 downto 0) Msg_data (7 downto 0) FROM REMOTE (TCLK) TO REMOTE (TCLK) FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK) Concentrator LX25 FPGA 2 x6 LX25 FPGA 2 x4

Trig_req (1 downto 0) Trig_val (1 downto 0) Lt_data (7 downto 0) Tv_data (7 downto 0) Lt_Strobe Tv_Strobe TRIGGER Handler serialized Trig_Rej (1 downto 0) 8 FANOUT TO OTHERS DEST 8 8 CORE MEZZANINE Local_Trigger (1 downto 0) MAIN FPGA LX25 GTS MEZZANINE FROM REMOTE (TCLK) Trig_req (1 downto 0) x4 TCLK

Trig_val (1 downto 0) Lt_data (7 downto 0) Tv_data (7 downto 0) Lt_Strobe Tv_Strobe Trig_Rej (1 downto 0) SERs / DESERs 8  1 GTS MEZZANINE cmc #1 Trig_req (1 downto 0) B_cast_data (7 downto 0) B_cast_str0 B_cast_str1 GTS Status (7 downto 0) pairs (20 lines) 44 lines TCLK 266 / 448 ~50% of LX25_FF668 Alignement BUS (3 lines) CMC #2CMC #3CMC #4FX100 TRIGGER & BCAST Handler (parallel)

Using 1 16 bit port : 128 words/event 256 bytes/event 6 channels  1536bytes 16bit 100MHz Need 7.68µs (20µs 50KHz) Serializer Data_A (15 downto 0) Empty_A Data_Ready_A Data_Request_A Deserializer 8 pairs ; 16 I/O 1Mx18 DPRAM 20bit Data readout engine Data_A (15 downto 0) Empty_A Data_Ready_A Data_Request_A X4 Mezzanines 18bit Serializer 20bit 18bit 1536*4 = 6144 byte/Event 16bit 200MHz Need 15.36µs (20µs 50KHz Max 325 Events stored Data Rate Required Data Readout Protocol Peak Bandwidth [Mb/sec] Peak Event Rate [KHz] Fast Ethernet [100Mbit/sec] G Ethernet [1.25 Gbit/sec] PCI Express [2.5 Gbit/sec]

MGT Clocking Layout RocketIO 101 MUX RocketIO 102 MUX RocketIO 103 MUX RocketIO 105 MUX MGTclk M34/N34 MGTclk AP28/AP29 RocketIO 106 MUX RocketIO 109 MUX RocketIO 110 MUX RocketIO 112 MUX RocketIO 113 MUX MGTclk AP3/AP4 MGTclk J1/K1 RocketIO 114 MUX 100  250MHz PCI Express JITTER ATTENUATOR 200MHz GTS Clock (***) User SFP could be used as 1GEnet or PCIExpress DAQ without FABRIC ATCA FABRIC CH15 ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB 100MHz GTS Clock OPTICAL SFP LOCAL 100MHz PHASE LOCKED ATCA FABRIC CHxx ATCA FABRIC CH13 ATCA FABRIC CH14 PCI Express SFP ATCA FABRIC CH02 ATCA FABRIC CH01 ATCA FABRIC CH04 ATCA FABRIC CH03 ATCA FABRIC CH06 ATCA FABRIC CH05 ATCA FABRIC CH12 ATCA FABRIC CH11 ATCA FABRIC CH10 ATCA FABRIC CH09 ATCA FABRIC CH08 ATCA FABRIC CH07

FPGA0 Temp MAX1617A Address $18 FPGA1 Temp MAX1617A Address $19 FPGA2 Temp MAX1617A Address $4C CMC1 Address $50 CMC2 Address $51 CMC3 Address $52 CMC4 Address $53 Temp Sens MAX6626 Address $48 Temp Sens MAX6626 Address $49 Temp Sens MAX6626 Address $4A SFP Lanes I2C Multiplexer MAIN FPGA (FX100) SFP Clock Temp Sens MAX6626 Address $4B FPGA1 Sw LX25 Address $60 FPGA2 Trigger LX25 Address $61 I2C Multiplexer DC-DC ATC210 Address ? I2C bus layout Fast Ethernet ATCA Zone1 IPMI IPMI Address IPMI A IPMI B uProcassor

JTAG Connector (Front Panel) MANUAL SW Slow control layout (JTAG Management) MAIN FPGA (FX100) JTAG SWITCH Fast Ethernet ATCA Zone1 IPMI IPMI Address IPMI A IPMI B I2C Multiplexer CONF[1..0] SEL PROGRAM [1..0] TCK TMS TDO INIT TDI X7 (4 Mezzanines + 3 FPGAs) RMT JTAG

TCLK Port Layout

ATCA Power Supply (maximum) Fusing -48V DC HS ENABLE DC to DC Converter DC to DC Converter DC to DC Converter DC to DC Converter P3V3-5A 16.5W MEZZANINE 1 MEZZANINE 2 MEZZANINE 3 MEZZANINE 4 MAIN BOARD P3V3-7A 23W P5V0/P2V5 Linear Reg M48/P12 DC P12/P3V3 DC MAIN BOARD P2V5-7A 17.5W P12/P2V5 DC FPGAs CORE P1V2-9A 11W P12/P1V2 DC FPGA MGT P1V2-5A 6W P5V0/P1V2 DC P5V0/P2V5 Linear Reg P2V5-1.0A P2V5-0.05A P5V0/P1V8 Linear Reg P1V8-0.5A PROMS VCCAUX Fpga 1 VCCAUX MGT P5V0/P2V5 Linear Reg P2V5-1.0A VCCAUX Fpga 2 P2V5/P1V5 Linear Reg P1V5-2.5A VTTTXs P2V5/P1V5 Linear Reg P1V5-0.2A VTTRXs MGT BUFFERS P1V8-4.2A 7.5W P5V0/P1V8 DC P12V-14.6A 181W P3V3-5A 16.5W M48V-4.2A 200W DC-DC Efficency assumed at least 90% DC-DC ARTESYN P3V3_BOOT DC-DC NATIONAL P12/P5V0 DC P5V0-8.6A 47.8W LINEAR REGULATORS P5V0/P1V5 Linear Reg P3V3-0.2A PLL_VCC P2V5/P1V8 Linear Reg P1V8-0.8A DPRAM_VCC P5V0/P3V3 Linear Reg P1V8-0.4A ZARLINK_VCC P2V5-4.8A 15.8W P5V0/P3V0 DC 8.3W P3V3-0.1A 18.2W 6.6W 10.8W 25.3W 19.3W 17.4W 2.0A (10W) 52.6W DC-DC POWER ONE SWITCH MICREL P2V5-2A 5W P1V8A VCCB P1V25A P2V5/P1V8 Linear Reg P0V8-0.8A DPRAM_VREF P5V0/P3V3 Linear Reg P3V3-0.6A SFP Power Supply P3V3_SFP_LANES P3V3_SFP_CLOCK IC95 VREF_DPRAM IC53 IC57 P1V8_DPRAM P3V3_ZLK P1V8_ZLK IC2 IC99 P3V3_CMC1 IC100 P3V3_CMC2 IC108 P3V3_CMC3 IC110 P3V3_CMC4 P3V3A IC49 IC78 P12V IC51 IC24 P1V2 IC92 P2V5 IC94 P3V3 IC16 IC15 IC10 P5V IC59 VTTTX_TILE1 VTTTX_TILE2 IC58 VTTRX IC48 IC54 P2V5A P2V5/P1V8 Linear Reg P0V8-0.8A P1V8_VCCO IC86 P2V5/P1V8 Linear Reg P2V5A_SW IC26 P2V5_AUX_FPGA0 IC45 IC42 P2V5_AUX_FPGA2 IC106 IC5 IC6 P1V8_FLASH0 P1V8_FLASH1 P1V8_FLASH2

1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress Case 1 : PCIExpress 1Mx36 DPRAM PRE PROCESSING ADCs TCLK Bus

1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM Case 2 : 1G Ethernet switch GEthernet Switch EB FARM PRE PROCESSING ADCs TCLK Bus

1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress Case 3 : PCIExpress (full mesh)