A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.
Outline Introduction Constrained via minimization problem Layer Assignment Algorithm Special consideration Experimental Flow and Results Conclusions and Future Work
Introduction Side effect of vias Chip area, Performance, Yield, Reliability Via minimization problem Two layer CVM, Multi-layer CVM Problem transformation Practical consideration
Basic Terminology Net Via Stacked via Mutually exclusive wire segments Connected wire segments M1 M3 Net 2Net 1 2 metal3 metal1 metal2 M2 1
Constrained Via Minimization (CVM) CVM-K problem n wire segments k different layers feasible assignment ( ) all design rules must be satisfied
Graph representation--G( ) Exclusive edge Connected edge Partitioning Cut Via Count exclusiveconnectedNode partitioning M1 M2 M3 M2M1 5 2
Problem Formulation Feasible partitioning Problem Transformation Quality of partitioning Feasible move K-way graph-partitioning problem M1 M2 M3 2 M1 M2 M3 2 M1 M2 M a b a: valid edge b: invalid edge 1 1 feasible moveinfeasible move
Feasible Partitioning with Illegal Via 1 3 M1 M2 M3 Illegal via for metal 1 and metal metal 1 metal 2 metal 3 exclusive connected Net 2 Net 1 2
Layer Assignment Algorithm Simulated Annealing-based Optimization Modification Random selection Sequential evaluation
Simultaneous Movement a1 a2 a1
Via Counting
Via Counting Example metal metal1metal metal 1 via_no + 1 no change Connected edge An example of via counting
An Observation Metal 1 Metal 2 Metal 3 Metal 1 Metal 2 Metal
Via Updating Partial modification An example 13 2 A B 13 2 A B 13 2 A B 1 Move node 1 to partition B Check node 2, mark 3 via_no + 1 Check node 3 via_no not changed
Special Consideration Overlap consideration I/O pin limitation Over-the-cell constraint a2 a1 Net 1 Net 2 a1 a2
Experimental Flow Input Technology Mapping (SIS) Cell Library Verilog-In automatic P&R Edif-Out Edif Parser Result Our algorithm with interlock solution Our algorithm w/o interlock solution
Experimental Results
Conclusions Formulating CVM-K problem as a constrained k-way graph partitioning problem Modified simulated annealing based heuristic High reduction ratio Apply to large circuits More effective than standard simulated annealing method
Future Work Crosstalk reduction Delay minimization Antenna Effect Consideration