System Overview MTT48 V Motorol a MOTOROLA 68HC08 INTRODUCTION AND SYSTEM OVERVIEW

System Overview MTT48 V Motorol a CONTENTS 68HC08 Micro Controller Family Evolution CSIC Design Philosophy CPU08 Overview 68HC708 Architecture Overview Module Preview 68HC08 Technical Support

System Overview MTT48 V Motorol a Motorola's 6800 Family Evolution Most Powerful Least Expensive HC11 60 Versions 68HC Versions 68HC08 15 Versions 68HC16 12 Versions MPC600 MPC & RISC 16-Bit8-Bit Versions 68HC12 2 versions Time Architecture Hardware Compatibility Software Compatibility

System Overview MTT48 V Motorol a Design Goals for 8-bit Microcontrollers Broad product offering for tiered performance application needs Higher performance, cost sensitive Easy migration path for existing 68HC05 users Ability to meet new customer requirements quickly Low voltage capable High quality, cost effective manufacturing capabilities Documentation and development support

System Overview MTT48 V Motorol a Motorola's Solution: The 68HC08 CPU HC05 object code compatible Architecturally enhanced 68HC05 CPU 5x average performance increase CSIC's first unified design rules (UDR) core New module based CSIC design/test methodology CPU architecture extensibility

System Overview MTT48 V Motorol a 68HC08 Modular CSIC Solution Modularity Requirements Standard internal bus definition Standard module heights Standard module definition Reduced Die Size (Cost-effectiveness) Individual modules hand packed to take up less silicon No excessive glue logic

System Overview MTT48 V Motorol a Building a CSIC from a Module Library MC68HC08 68HC08 CPU MEM GEN PTAPTB PTCPTD ADXSIMDMACPU CSIC LIBRARY CPM EXT BUS TIM PLL RTC OSC OSD SCI PWM LCD SPI A/D CPM – CUSTOMER PROPRIETARY MODULE

System Overview MTT48 V Motorol a HC05 Single Chip Operation (except for 68HC05C0) No Direct Control of the Stack Pointer One 8-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL Instruction IDR Process (4Mhz bus) HC11 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions Two 16-Bit Index Register Two 8-Bit Accumulator or One 16-Bit Accumulator 16-Bit Math with MUL and DIV instructions IDR P Process (4 Mhz bus) HC08 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions One 16-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL and DIV Instructions UDR Process (8 Mhz bus) 68HCxx 8-BIT CPU Cores Major Differences

System Overview MTT48 V Motorol a Let's take a closer look at the CPU 68HC08 CPU System Integration Module Clock Generation Module Timer Module Peripheral Module Peripheral Module Peripheral Module RAM Memory ROM Type Memory Internal Bus (IBUS) LVI Module COP Module DMA Module BREAK Module IRQ Module RESET Module Peripheral Module

System Overview MTT48 V Motorol a 68HC08 CPU Design Accomplishments Increased Bus Speed of 8Mhz at 5V Sub-micron UDR process Improved Instruction Set and Addressing Modes Opcode Look-Ahead Instruction Prefetch Optional Modular Extensions DMA module reduces interrupt overhead Address extension module increases address bus to 24- bits for > 64K data/program space

System Overview MTT48 V Motorol a 68HC08 Instruction Preview Data Movement Load, Store, Move, Stack Arithmetic Add, Sub, Mul, Div Logical And, Or, Eor Data and Bit Manipulation Shifts, Rotates, Bit Test Program Control Branch, Subroutine Binary Coded Decimal Looping Constructs Special High Level Language Support

System Overview MTT48 V Motorol a 68HC08 Addressing Preview Inherent Immediate Direct Extended Indexed 8 and 16 bit offset Stack Pointer Post Increment Relative Memory to Memory Direct Indexed

System Overview MTT48 V Motorol a 68HC08 Instruction/Addressing Summary Stack Manipulation (48 new instructions) –Directly push/pull any register & add immediate to stack –Stack relative addressing mode –Temporary variables on the stack can be manipulated directly, without loading them into the accumulator Index Extension Register (7 new instructions) –Allows use of full 16-bit index register (H:X) Memory to Memory Move (4 new instructions) Looping Constructs (12 new instructions) –Decrement and Branch –Compare and Branch Arithmetic Enhancements (1 new instruction) –Faster multiply (5 clks vs 11) –Divide (16/8) BCD Support (2 new instructions) –Decimal adjust accumulator and nibble swap accumulator C Compiler Support (4 new instructions) –Conditional branch with signed operands

System Overview MTT48 V Motorol a 68HC08 Flagship MC68HC708XL36 Architecturally Enhanced 8-bit CPU 1Kbyte RAM and 36Kbytes EPROM 240 Bytes Monitor ROM System Control and Protection Modules (SIM) Direct Memory Access Module (DMA) General Purpose Timing Interface Module (TIM) Serial Communication Modules (SCI and SPI) 68HC08 CPU System Integration Module Clock Generation Module Timer Interface Module Direct Memory Access Module Serial Communications Interface Internal Bus (IBUS) Serial Peripheral Interface Random Access Memory Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET

System Overview MTT48 V Motorol a CPU SYSTEM MODULES ³Low Voltage Inhibit (LVI) ³Computer Operating Properly (COP) ³Break Module ³External Interrupt Module (IRQ) ³System Integration Module (SIM) Manages System Protection –Reset on illegal address and illegal opcode –Optional reset on LVI and COP Manages Interrupts with up to 128 separate vectors Bus Clock Generation for CPU and most Peripherals CLOCK GENERATION MODULE(CGM) ³Provides clock inputs into SIM Module and SCI Baud Generator ³Crystal Oscillator circuit and phase locked loop circuit Avoids the cost and noise of high frequency crystals ³Programmable bus frequency Integer multiples (1 to 15) of crystal frequency ÷ 4 TIMING INTERFACE MODULE (TIM) ³Modular architecture ³68HC05C4 timer compatible channels Input capture, Output Compare, PWM ³Counter may be free-running or modulo up-counter Optionally toggle any channel output on overflow ³Timer interrupts can select CPU or DMA servicing

System Overview MTT48 V Motorol a DIRECT MEMORY ACCESS (DMA) ³DMA can be used to reduce CPU overhead of processing normal data movement interrupts ³Using DMA to service peripherals instead of CPU interrupts can dramatically reduce interrupt overhead A byte transfer takes only two clocks (4 MByte/sec peak) CPU processing continues after the DMA transfer as if nothing happened ³Allows transfers between any two CPU addressable locations ³Expandable architecture up to seven channels ³Block transfer capability of up to 256 bytes ³Programmable bus bandwidth utilization of 25% to 100% ³Optional CPU interrupt upon completion data block transfer ³Optional enable for DMA operation during low power wait SERIAL PERIPHERAL INTERFACE (SPI) ³Compatible with HC05 SPI but with enhancements: Separate receive and transmit buffers avoid write collisions Programmable wired-or mode DMA can service normal data movement SPI interrupts

System Overview MTT48 V Motorol a SERIAL COMMUNICATIONS INTERFACE (SCI) ³Compatible with HC05 SCI but with enhancements: Optional HW parity Two idle line receiver wakeup methods Additional interrupt vectors and interrupt enables Loop mode for diagnostics/test DMA can service normal data movement SCI interrupts MEMORY MODULES ³1 KByte fully static 8-bit RAM ³36 KBytes of 8-bit user-programmable ROM Windowed packages available for UV erasure One-time programmable non-windowed packages EPROM security mode

System Overview MTT48 V Motorol a New Module Development Modules currently in design or targeted2, 6, & 8 Channel Programmable Timers Dedicated 8-bit & 16-bit Pulse Width Modulation Analog/Digital Converter (8-bit and 10-bit) External Bus Interface Address Extension Comparators RAM EPROM ROM EEPROM I 2 C LCD Customer Specific OSD - On Screen Display

System Overview MTT48 V Motorol a 68HC08 Summary Architecture is an extension of the world's leading 8-bit microcontroller family - 68HC05 Offers a high performance, cost-effective migration for existing HC05 applications Modular design and test methodology gives Motorola ability to meet customer new product requirements with dramatically lower cycle time Supported by a portfolio of development tools to program, evaluate and design applications