The MIPS 32 1)Project 1 Discussion? 1)HW 2 Discussion? 2)We want to get some feel for programming in an assembly language - MIPS 32 We want to fully understand the context frames and switching 4)We want to discuss arithmetic - multiplication and division instructions Note: Anyone want to work in the lab (for $ )?

Switch Debouncing  An excellent switch debounce circuit: - inputs S, R, D, & C are always a “0” or a “1” Up = 1, Down = 0 Up = 0, Down = 1 1K – 5 K

An Asside  What is a MIPS 32 pseudoinstruction ? - an instruction that is not a “real” MIPS 32 instruction but is assembled into a “real” machine language instruction. - example: move rd, sr assembles like add rd, sr, $0

Procedure Call “Convention” Before calling a routine, the caller must: What Registers MUST the callee routine save? What Registers MUST the caller routine save? What should be the size of the frame? Minus 4

MIPS Register Convention NameRegister Number UsagePreserve on call? $zero0constant 0 (hardware)n.a. $at1reserved for assemblern.a. $v0 - $v12-3returned valuesno $a0 - $a34-7argumentsyes $t0 - $t78-15temporariesno $s0 - $s716-23saved valuesyes $t8 - $t924-25temporariesno $gp28global pointeryes $sp29stack pointeryes $fp30frame pointeryes $ra31return addr (hardware)yes

Example Program

Main Routine Callee Duties Caller duties Print results Callee Duties

Called Routine Callee duties Routine algorithm Caller duties Callee duties

Arithmetic Operations  Add & Subtract – Can they be done in one cycle? - How can add/sub speed be improved? - How does MIPS handle overflow?  Multiplication & Division – How long do they take? - How can mult/div speed be improved? - What are Registers LO and Hi ?

Multiply  Binary multiplication is just a bunch of right shifts and adds multiplicand multiplier partial product array double precision product n 2n n can be formed in parallel and added in parallel for faster multiplication

Multiplication

Shift & Add simultaneously:

Multiplication Multiple Adders:

Division  Division is just a bunch of quotient digit guesses and left shifts and subtracts dividend divisor partial remainder array quotient n n remainder n

Division

Shift & Add simultaneously:

IEEE 754 FP Standard Encoding  Most (all?) computers these days conform to the IEEE 754 floating point standard (-1) sign x (1+F) x 2 E-bias l Formats for both single and double precision l F is stored in normalized form where the msb in the fraction is 1 (so there is no need to store it!) – called the hidden bit l To simplify sorting FP numbers, E comes before F in the word and E is represented in excess (biased) notation Single PrecisionDouble PrecisionObject Represented E (8)F (23)E (11)F (52) 0000true zero (0) 0nonzero0 ± denormalized number ± 1-254anything± anything± floating point number ± 2550± 20470± infinity 255nonzero2047nonzeronot a number (NaN)

Floating Point Addition  Addition (and subtraction) (  F1  2 E1 ) + (  F2  2 E2 ) =  F3  2 E3 l Step 1: Restore the hidden bit in F1 and in F2 l Step 1: Align fractions by right shifting F2 by E1 - E2 positions (assuming E1  E2) keeping track of (three of) the bits shifted out in a round bit, a guard bit, and a sticky bit l Step 2: Add the resulting F2 to F1 to form F3 l Step 3: Normalize F3 (so it is in the form 1.XXXXX …) -If F1 and F2 have the same sign  F3  [1,4)  1 bit right shift F3 and increment E3 ? -If F1 and F2 have different signs  F3 may require many left shifts each time decrementing E3 ? l Step 4: Round F3 and possibly normalize F3 again l Step 5: Rehide the most significant bit of F3 before storing the result

Floating Point Addition Hardware

Reflecting What resources/knowledge is needed to program in a new Machine/Assembly Language ?  ?