CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

CML CMLAnnouncements Project 3 –MIPS Assembler Midterm Reviews Quiz 4 –Nov 5, 2009 –Single-cycle implementation Finals –Tuesday, Dec 08, 2009

CML CML What is this? MIPS machine language code for a routine to compute and print the sum of the squares of integers between 0 and 100. int main (int argc, char *argv[]) { int i; int sum = 0; for (i = 0; i <= 100; i = i + 1) sum = sum + i * i; printf ("The sum from is %d\n", sum); }

CML CML Abstract Implementation View Two types of functional units: –elements that operate on data values (combinational) –elements that contain state (sequential) Single cycle operation Split memory (Harvard) model - one memory for instructions and one for data AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

CML CML Fetching Instructions Fetching instructions involves –reading the instruction from the Instruction Memory –updating the PC to hold the address of the next instruction –PC is updated every cycle, so it does not need an explicit write control signal –Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal Read Address Instruction Memory Add PC 4

CML CML Executing R Format Operations R format operations ( add, sub, slt, and, or ) –perform the indicated (by op and funct) operation on values in rs and rt –store the result back into the Register File (into location rd) –Note that Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: oprsrtrdfunctshamt 10

CML CML Load and Store Operations Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

CML CML Executing Branch Operations Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

CML CML Executing Jump Operations Jump operations have to –replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Shift left 2 Jump address J-Type: op jump target address Add 4 PC

CML CML Adding the Pieces Together MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

CML CML Adding the Branch Portion Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc

CML CML 26 Adding the Jump Portion Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc 0 1 Shift left 2 Jump 28 PC+4[31-28] 32

CML CML 26 Instr[25-0] MIPS Machine (with Controls) Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 PC+4[31-28] 28

CML ALU Control ALU control inputFunction 000and 001or 010add 110subtract 111set on less than  ALU's operation based on instruction type and function code result 32 operation a b ALU

CML ALU Control Controlling the ALU makes use of multiple levels of decoding –main control unit generates the ALUOp bits –ALU control unit generates ALU control inputs Instr opopcodefunctALUOpdesired action ALU control input lw23xxxxxx00add010 sw2bxxxxxx00add010 beq4xxxxxx01subtract110 add add010 subt subtract110 and and000 or or001 slt slt111

CML ALU Control Truth Table Can make use of more don’t cares –since ALUOp does not use the encoding 11 –since F5 and F4 are always 10 Logic comes from the K-maps … X X X X X X F5F4F3F2F1F0ALUOp1ALUOp0Op2Op1Op0 XXXXXX00010 XXXXXX1110 XX XX XX XX XX

CML CML ALU Control Combinational Logic From the truth table can design the ALU Control logic

CML CML Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CML CML Main Control Unit InstrRegDstALUSrcMemtoRegRegWrMemRdMemWrBranchALUOp1ALUOp2 R-type lw sw beq  Completely determined by the instruction opcode field l Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

CML CML R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CML CML Main Control Unit InstrRegDstALUSrcMemtoRegRegWrMemRdMemWrBranchALUOp1ALUOp0 R-type X001X lw sw beq

CML CML Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CML CML Main Control Unit InstrRegDstALUSrcMemtoRegRegWrMemRdMemWrBranchALUOp1ALUOp0 R-type X001X lw sw beq

CML CML Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CML CML Main Control Unit InstrRegDstALUSrcMemtoRegRegWrMemRdMemWrBranchALUOp1ALUOp0 R-type X001X lw sw X1X0X1000 beq

CML CML Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CML CML Main Control Unit Completely determined by the instruction opcode field –Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation InstrRegDstALUSrcMemtoRegRegWrMemRdMemWrBranchALUOp1ALUOp0 R-type X001X lw sw X1X0X1000 beq X0X0X01X1

CML CML Control Unit Logic From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lwswbeq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0

CML CML Complete Datapath with Controls Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CML CML Disadvantages of Single Cycle Implementation Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction –especially problematic for more complex instructions like floating point multiply Is wasteful of area since some functional units must be duplicated since they can not be “shared” during an instruction execution –e.g., need separate adders to do PC update and branch target address calculations, as well as an ALU to do R- type arithmetic/logic operations and data memory address calculations

CML CML Yoda says… Use your feelings, Obi-Wan, and find him you will