Parul Polytechnic Institute Parul Polytechnic Institute Subject Code : 3330705 Name Of Subject : Microprocessor and assembly language programming Name.

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Parul Polytechnic Institute Parul Polytechnic Institute Subject Code : Name Of Subject : Microprocessor and assembly language programming Name of Unit : Introduction to Microprossor Topic : The 8085 Microprocessor Architecture Name of Faculty : H.M.Avaiya & N.D.Dhameliya Name of Students: (i) MACHHI DIVYA D(020) (ii) THAKKAR ROSHNI K(021)

Timing diagram of memory read & write operation

Timing operation The 8085 performs 4 primary operation The 8085 performs 4 primary operation 1.Memory read 2.Menory write 3.I/O read 4.I/O write These operations are part of communication between the 8085 and peripherals. These operations are part of communication between the 8085 and peripherals.

Performance of 8085 The 8085 performs 3 steps The 8085 performs 3 steps 1. To identify the memory location by 16- bit address for memory operation and I/O devices by port address for I/O operation. 2. Transfer the data 3. Provide the necessary control signals like _____ ______ ____ _____ ______ ____ MEMR, MEMW, IOR etc. MEMR, MEMW, IOR etc.

Timing diagram

Timing diagram theory The 8085 require 3 T-state to complete the memory read operation. The 8085 require 3 T-state to complete the memory read operation. During T1,ALE goes high and the 8085 places the higher –order address on A15 –A8 and lower order address on AD-AD0 During T1,ALE goes high and the 8085 places the higher –order address on A15 –A8 and lower order address on AD-AD0 The higher value of ALE indicates the availability of address on multiplexed address/data bus AD7-AD0. The higher value of ALE indicates the availability of address on multiplexed address/data bus AD7-AD0. ___ ___ The lower value of IO/ M indicates the memory operation. The lower value of IO/ M indicates the memory operation. The end of T1. Ale goes low which latches the lower order address into the latch and makes the bus free for data transfer. The end of T1. Ale goes low which latches the lower order address into the latch and makes the bus free for data transfer. ___ ___ ___ ___ During T2, RD signal goes low which together with IO/ M During T2, RD signal goes low which together with IO/ M ______ ______ generate the control signal MEMR.

Con… To communicate with the I/O devices, the 8085 performs I/O operations like I/O read and I/O write. To communicate with the I/O devices, the 8085 performs I/O operations like I/O read and I/O write. ___ ___ The high value of IO/ M is used to indicate the I/O operations, the The high value of IO/ M is used to indicate the I/O operations, the ___ ___ ____ ____ ____ RD and WR signals are used with IO/ M = 1 to generate IOR & IOW Control signals required to complete the I/O read and I/O write operations.