9/15/05ELEC5970-001/6970-001 Lecture 71 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Slides:



Advertisements
Similar presentations
Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore
Advertisements

Topics Electrical properties of static combinational gates:
Digital Integrated Circuits© Prentice Hall 1995 Low Power Design Low Power Design in CMOS.
10/4-6/05ELEC / Lecture 111 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
ELEC Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.
Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.
Digital Integrated Circuits A Design Perspective
CMOS Digital Integrated Circuits
Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch5. CMOS Performance Factors.
Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.
8/29/06 and 8/31/06 ELEC / Lecture 3 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage.
10/27/05ELEC / Lecture 161 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
10/25/05ELEC / Lecture 151 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
11/01/05ELEC / Lecture 171 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
11/03/05ELEC / Lecture 181 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Spring 07, Feb 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Reducing Power through Multicore Parallelism Vishwani.
9/01/05ELEC / Lecture 41 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
9/08/05ELEC / Lecture 51 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
8/22/06 and 8/24/06 ELEC / Lecture 2 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Power.
Digital Integrated Circuits A Design Perspective
8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani.
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power.
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices Vishwani.
8/30/05ELEC / Lecture 31 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
9/20/05ELEC / Lecture 81 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Logical Effort.
CMOS Digital Integrated Circuits 1 Lec 7 CMOS Inverters: Dynamic Analysis and Design.
9/13/05ELEC / Lecture 61 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal.
© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Digital Workhorse  Best Figures of Merit in CMOS Family  Noise Immunity  Performance  Power/Buffer.
8/18/05ELEC / Lecture 11 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Fall 2006, Nov. 28 ELEC / Lecture 11 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: High-Level.
10/13/05ELEC / Lecture 131 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
10/11/05ELEC / Lecture 121 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
9/29/05ELEC / Lecture 101 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Fall 2006, Oct. 17 ELEC / Lecture 9 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: Logic Level.
8/23-25/05ELEC / Lecture 21 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino.
10/20/05ELEC / Lecture 141 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Fall 06, Sep 14 ELEC / Lecture 5 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC / )
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 6 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing Vishwani.
Digital Integrated Circuits A Design Perspective
Fall 2006: Dec. 5 ELEC / Lecture 13 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani.
CMOS VLSI For Computer Engineering Lecture 4 – Logical Effort Prof. Luke Theogarajan parts adapted form Harris – and Rabaey-
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 11 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.
1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.
Review: CMOS Inverter: Dynamic
1. Department of Electronics Engineering Sahand University of Technology NMOS inverter with an n-channel enhancement-mode mosfet with the gate connected.
Elmore Delay, Logical Effort
Chapter 07 Electronic Analysis of CMOS Logic Gates
CMOS Inverter: Dynamic V DD RnRn V out = 0 V in = V DD CLCL t pHL = f(R n, C L )  Transient, or dynamic, response determines the maximum speed at which.
Inverter Chapter 5 The Inverter April 10, Inverter Objective of This Chapter  Use Inverter to know basic CMOS Circuits Operations  Watch for performance.
EE141 © Digital Integrated Circuits 2nd Inverter 1 Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje.
Spring 2010, Mar 10ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing Vishwani D. Agrawal James J. Danaher.
Switch Logic EE141.
Digital Integrated Circuits A Design Perspective
© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 A few notes for your design  Finger and multiplier in schematic design  Parametric analysis.
CSE477 L11 Fast Logic.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 11: Designing for Speed Mary Jane Irwin (
ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.
ELEC Digital Logic Circuits Fall 2014 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.
Damu, 2008EGE535 Fall 08, Lecture 51 EGE535 Low Power VLSI Design Lecture #5 & 6 CMOS Inverter.
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher.
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher.
ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher.
CSV881: Low-Power Design Multicore Design for Low Power
ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher.
ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing
ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher.
Presentation transcript:

9/15/05ELEC / Lecture 71 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Transistor Sizing Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

9/15/05ELEC / Lecture 72 Delay of a CMOS Gate CMOS gate CLCL CgCg C int Propagation delay through the gate: t p = 0.69 R eq (C int + C L ) ≈ 0.69 R eq C g (1 + C L /C g ) = t p0 (1 + C L /C g ) Gate capacitance Intrinsic capacitance

9/15/05ELEC / Lecture 73 R eq, C g, C int, and Width Sizing R eq : equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor C g : gate capacitance, proportional to C ox WL; scales as S C int : intrinsic output capacitance ≈ C g, for submicron processes t p0 : intrinsic delay = 0.69R eq C g ; independent of sizing

9/15/05ELEC / Lecture 74 Effective Fan-out, f Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f=C L /C g t p =t p0 (1 + f )

9/15/05ELEC / Lecture 75 Sizing an Inverter Chain Cg1Cg1 Cg2Cg2 CLCL 12N C g2 = f2C g1 t p1 = t p0 (1 + C g2 /C g1 ) t p2 = t p0 (1 + C g3 /C g2 )N t p =Σ t pj =t p0 Σ (1 + C gj+1 /C gj ) j=1j=1

9/15/05ELEC / Lecture 76 Minimum Delay Sizing Equate partial derivatives of t p with respect to C gj to 0: 1/C g1 – C g3 /C g2 2 = 0, etc. C g2 2 = C g1 ×C g3, etc. C g2 /C g1 = C g3 /C g2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: C L /C g1 = F = f N, t p = Nt p0 (1 + F 1/N )

9/15/05ELEC / Lecture 77 Minimum Delay Sizing Equate partial derivatives of t p with respect to N to 0: dNt p0 (1 + F 1/N ) ───────── = 0 dN i.e. F 1/N – F 1/N (ln F)/N = 0 or ln f = 1 → f = e = 2.7 and N = ln F

9/15/05ELEC / Lecture 78 Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003.

9/15/05ELEC / Lecture 79 Sizing for Energy Minimization Cg1Cg1 CLCL t p = t p0 [(1+f) + (1+F/f )] = t p0 (2+ f + F/f ) F= C L /C g1 t p0 ~V DD /(V DD - V t ) Energy dissipation, E = V DD 2 C g1 (1 + f + F ) f 1

9/15/05ELEC / Lecture 710 Holding Delay Constant Reference circuit: f = 1, supply voltage = V ref Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: t p t p0 (2+f+F/f ) V DD V ref -V t 2+f+F/f ── = ──────── = ── ──── ───── ≤ 1 t pref t p0ref (3+F ) V ref V DD -V t 3+F

9/15/05ELEC / Lecture 711 Supply Voltage Vs. Sizing f V DD (volts) F= f opt ≈ √F V ref = 2.5V V t = 0.5V

9/15/05ELEC / Lecture 712 Energy E V DD f + F ── = ─── ────── E ref V ref F

9/15/05ELEC / Lecture 713 Normalized Energy Vs. Sizing f Normalized Energy F= f opt ≈ √F V ref = 2.5V V t = 0.5V

9/15/05ELEC / Lecture 714 Summary Device sizing combined with supply voltage reduction reduces energy consumption. For large fan-out energy reduction by a factor of 10 is possible. An exception is F = 1 case, where the minimum size device is also the most effective one. Oversizing the devices increases energy consumption.