Digital Logic with VHDL EE 230 Digital Systems Fall 2006 (10/17/2006)

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Presentation transcript:

Digital Logic with VHDL EE 230 Digital Systems Fall 2006 (10/17/2006)

A Simple Logic Function f x 3 x 1 x 2 ENTITY myfunctionf IS PORT ( x1, x2, x3 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END myfunctionf ; ARCHITECTURE Behavioral OF myfunctionf IS BEGIN f <= (x1 AND x2) OR (NOT x2 AND x3) ; END Behavioral ;

ISE VHDL Project Setup

VHDL New Source

Define Input/Output

Simulation Results X 3 X 2 X 1 =010, f=0 X 3 X 2 X 1 =100, f=1

Combine Signals for Readability

More… LIBRARY ieee ; USE ieee.std logic_1164.all ; ENTITY func1 IS PORT ( x1, x2, x3 : IN STD_LOGIC ; f : OUT STD_ LOGIC ) ; END func1 ; ARCHITECTURE LogicFunc OF func1 IS BEGIN f <= (NOT x1 AND NOT x2 AND NOT x3) OR (NOT x1 AND x2 AND NOT x3) OR (x1 AND NOT x2 AND NOT x3) OR (x1 AND NOT x2 AND x3) OR (x1 AND x2 AND NOT x3) ; END LogicFunc ;

Hierarchy/Modularize Design LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY myfulladder IS PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END myfulladder ; ARCHITECTURE Behavioral OF myfulladder IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END Behavioral;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT myfulladder PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT; BEGIN stage0: myfulladder PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: myfulladder PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: myfulladder PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: myfulladder PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ; 4-bit Adder

16-bit Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( X, Y: IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

2-to-1 Mux LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, s: IN STD_LOGIC ; f: OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <=w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

4-to-1 Mux LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;