1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems part 5: Special and weird ‘processor’ types dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

1/1/ / faculty of Electrical Engineering eindhoven university of technology A single superinstruction, > 100 bits long: Very Large Instruction Word machines VLIW machines use ‘super-instructions’ which explicitly control all functional units in parallel integer 1integer 2load/storefloating pt.jump/call To the functional units... –All scheduling must be done by compiler –Unused sub-instructions must be ‘No operation’ Trimedia: variable length instructions

1/1/ / faculty of Electrical Engineering eindhoven university of technology Single Instruction-Multiple Data machines Lots of ALU’s performing the same operation Systolic array: –Number of ALU’s equals number of data elements –Can have local storage and neighbour connections Vector processor: –Number of ALU’s below number of data elements –Lack of dependencies allows VERY fast pipelines Intel’s MMX is a kind of SIMD !

1/1/ / faculty of Electrical Engineering eindhoven university of technology column address ‘Intelligent memory’ SIMD machines Uses layout and technology of modern RAM chips to get massive parallellism row address 2-D memory bits cell array read one bitwrite one bit ‘row’ select ‘column’ bit line (leaky) capacito r read row write/’refresh’ row read/write amplifiers and data latches parallel one- bit ‘processors’ column addres s control ALU, carry bit, local storage bits, global AND/OR test, left/right neighbour communication takes < 20% extra chip area !

1/1/ / faculty of Electrical Engineering eindhoven university of technology  (A+B) (C–D) (A+B)  (C–D) Dataflow processing It is possible to write functions like (A + B)  (C – D) as an Acyclic Directed Graph +– A A B B C C D D ‘arc’s carry (intermediate) data values ‘node’s perform actual operations ‘dataflow graph’

1/1/ / faculty of Electrical Engineering eindhoven university of technology Dataflow graph memory and decisions These functions require special node types ! read address read data write address data to write A A A (>15) nil (<= 15) T nil (> 15) A (<= 15) F decision: A > 15 memory node EXAMPLES !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Dataflow processor architecture packet grouping and operation selection packet buffers (RAM) routing using packet ID input data_1 data_2 operation/ID out (universal) ALU’s data_1 data_2 operation/ID out output Data stored in ‘packets’ (‘tokens’) with arc ID graph structure memory & queuein g arbitration & schedulin g node operations (abstract) EXAMPLE !

1/1/ / faculty of Electrical Engineering eindhoven university of technology A ‘fuzzy logic’ example rule-set Control the brakes of a car with a radar sensor 1)IF (  V negative) THEN do not brake 2)IF (  V low AND D large) THEN do not brake 3)IF (  V low AND D small) THEN brake gently 4)IF (  V high AND D large) THEN brake gently 5)IF (  V high AND D small) THEN brake strongly Measuring frequency shift gives speed difference  V (due to Doppler effect) Measuring transit time gives distance D

1/1/ / faculty of Electrical Engineering eindhoven university of technology – relative speed  V (km/hr) +50 Fuzzy sets, or, ‘what is high and low?’ A fuzzy set classifies a ‘scalar’ value as a set of ‘truth values’ in the range 0..1 Truth: 0 Truth: 1 ’  V negative''  V low''  V high' distance D (m) Truth: 0 Truth: 1 ’D small'’D large' Needed for smooth braking (switch between rules 1 and 3) ‘still low, but also a bit high’

1/1/ / faculty of Electrical Engineering eindhoven university of technology Rewriting logic into fuzzy rules Replace AND by MIN(imum), OR by MAX(imum) Combine rules 1 & 2 using normal logic: do not brake IFF (  V negative) OR (  V small AND D large) Combination of rules 1 & 2 in fuzzy logic: do not brake := MAX(  V negative, MIN(  V small, D large)) Combination of rules 3 & 4 in fuzzy logic: brake gently := MAX(MIN(  V low, D small), MIN(  V high, D large)) Rule 5 in fuzzy logic: brake strongly := MIN(  V high, D small)

1/1/ / faculty of Electrical Engineering eindhoven university of technology From fuzzy sets back to scalar values 05Braking force (m/s 2 ) Truth: 0 Truth: 1 ’do not brake'’brake gently'’brake strongly' How to calculate scalar value ‘Braking force’ from fuzzy set ’do not brake' = 0.2, ’brake gently' = 0.8 and ’brake strongly' = 0.4 1:scale fuzzy set graphs to their truth values 2:calculate centre of gravity and surface area under the individual scaled graphs 3:calculate weigthed sum of centre of gravities and its position 4:read scalar result value as position of weighted sum along the X-axis 3:calculate weigthed sum of centre of gravities and its position

1/1/ / faculty of Electrical Engineering eindhoven university of technology Fuzzy logic processors Non time-critical applications: normal processors –Compilers exist: fuzzy set + logic rules  C program Fuzzy logic rules (‘MIN’/’MAX’) processors exist –Sometimes include scalar  fuzzy set conversion –Almost never include fuzzy set  scalar conversion –Advantageous to build them as dataflow machine Fuzzy logic calculations need not be very precise –Possible to build ‘processor’ with analog electronics !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Massive parallel fuzzy: neural networks Example: handwriting recognition feature extract feature combin e decide and encode (hex) = ASCII ‘A’ Lots of inputs, fewer outputs: each output is combination of inputs a neuron (one of many) Neural network with three layers of neurons

1/1/ / faculty of Electrical Engineering eindhoven university of technology A single neuron Constants can be negative –‘Inhibit’ or ‘blocking’ input Transfer function can have many forms  c1  c2  c3  cn  inputs output Multiply by constant Sum multiply results Transfer function: decide, scale & clip Implemented like fuzzy –Neural to C compiler –Dataflow architecture No high precision needed –Analog electronics possible Can be made self- learning