Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering EE 333 Exam 2 November 10, 2005 Instructions 1.Print your name, student ID, and seat in the above blanks. 2.This is a Closed Book exam. 3.Do all of the problems. They may vary in points but the total is 100. Questions are short answer and problems. 4.Do not use any additional pages of paper. If you run out of room, use the back sides. Do not remove the staple. 5.Please write clearly or print. Illegible or unreadable answers may not be graded for partial credit. 6.Mark your answer with a box or star Name Student ID Seat Answers

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 1 (10 pts) For the MIPS datapath, what are the five instruction steps and what they do? 1)IF: read instruction into IR, increment PC by 4 2)ID: read registers, find optimistic branch address 3)EX: function, effective address, possible PC change 4) MEM: read or write memory 5) WB: write register file

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 2 (10 pts) 1.What is an effective address? Used to reference memory 2.What is an optimistic branch address? Its written to the PC conditionally 3.What is a jump address? Its always written to the PC 4.What is a word-aligned address? Two lsb’s are zero 5.What is a concatenated address? Upper and lower bits come from different sources

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 3 (10 pts) Determine the control signals for the load word MEM clock? Mark on the next page. Operation (lw) –Mem Data Reg = Memory [ALUout] Functional units –ALUout addresses memory –Load: memory read and data clocked into MDR

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 3 (10 pts), continued.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 4 (10 pts) Consider the state diagram at left

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 4 (10 pts), continued. InstClk 1Clk 2Clk 3Clk 4Clk 5 or $1, $2, $30167 j loop019 beq $1, $4, done018 sw $4, 64($5)0125 and $8, $12, $ Determine the state transitions ?

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 5 (10 pts) Consider the Signal definitions: Din = 16-bit data input Write = Data at Din written to register(s), 2 bits Read0, Read1 = Determines the register to read, 2 bits R0Out, R1Out = 16-bit data output

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 5 (10 pts), continued. Sketch the architecture of a register file with four, 16-bit registers, 2 read ports, 1 write port using decoder, MUX, and D registers, include Reg A and B.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 6 (10 pts) A.Describe the Principle of Locality? Programs access a relatively small portion of their address space at any instant of time B.Explain the features of a memory hierarchy? Memory closer to the CPU is faster, more expensive, and smaller. Memory further from the CPU is slower, less expensive, and bigger.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 7 (10 pts) Determine the length and width of the memory components required for the system memory in the table below (note: G=1024M, M=1024K)? MemoryComponentLengthWidth 16K x 162K x K x 3216K x M x 32256K x M x 641M x G x 64512M x 888

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 8 (10 pts) Complete the 32x8 RAM design; fully decode for 0x00 start address.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 9 (10 pts) CPU writeCache write adrdatatagadrdata x x x x xaaa011110xaaa x x xabc100010xabc Find the final cache contents. Assume a 32 byte memory, 8 byte write-through cache.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Problem 10 (10 pts) Find an expression for the average latency L of a memory and write-back cache hierarchy? Assume the hit rate is h, memory latency is m, the cache latency is c, and the probability of a modified cache miss is d.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering Statistics ProbStdAve 1/ / / / / / / / / / Ave