系 統 程 式 System Programming

Slides:



Advertisements
Similar presentations
Introduction – This book introduces to the design and implementation of System Software
Advertisements

System Programming Design and Implementation of system software.
Chapter 11 Implementing an Assembler and a Linker Using C++ and Java.
Week 3. Assembly Language Programming  Difficult when starting assembly programming  Have to work at low level  Use processor instructions >Requires.
10/9: Lecture Topics Starting a Program Exercise 3.2 from H+P Review of Assembly Language RISC vs. CISC.
System Programming 09:10-12:00 Friday T Instructor Quincy Wu ( 吳坤熹 ), Textbook Leland L. Beck, "System.
Instruction Set Architecture
Welcome to Systems Software The purpose of this course is to provide background in fundamental types of system software, particularly assemblers, loaders,
1 System Programming System Software, pp Chia-Hui Chang, Assistant Professor Dept. of Computer Science & Information Engineering National Central.
The Simplified Instructional Computer (SIC/SICXE)
1: Background1 System Programming ( 系統程式 ) Main goal: r What is a system software? m Compiler m Assembler m Loader and Linker m Debugger… r To design and.
Simplified Instructional Computer (SIC). SIC Architecture Two versions: SIC and SIC/XE (extra equipments). SIC program can be executed on SIC/XE. Memory.
SYSTEM SOFTWARE Dr.A.KANNAN, PROFESSOR & HEAD, DEPARTMENT OF IST CS2304.
System Software by Leland L. Beck chapter 1, pp.1-20.
Chapter 1 Background System Software Chih-Shun Hsu
1 Chapter 1 Background Professor Gwan-Hwan Hwang Dept. Computer Science and Information Engineering National Taiwan Normal University 9/17/2009.
1 The Simplified Instructional Computer (SIC) Hsiang-Fu Yu National Taipei University of Education.
System Software.
System Software by Leland L. Beck chapter 1, pp.1-20.
System Programming Chih-Hung Wang Chapter 1: Background (Part-1) 參考書目
Low-Level Programming Languages
CSCE 121, Sec 200, 507, 508 Fall 2010 Prof. Jennifer L. Welch.
Instruction Representation II (1) Fall 2007 Lecture 10: Instruction Representation II.
Chapter 7 Low-Level Programming Languages. 2 Chapter Goals List the operations that a computer can perform Discuss the relationship between levels of.
Chapter 7 Low-Level Programming Languages Nell Dale John Lewis.
Programmable System on Chip Fully Configurable Mixed Signal Array Allows for Completely Customizable System Designs Capable of Internal MCU.
Chih-Hung Wang Chapter 1: Background (Part-1) 參考書目 Leland L. Beck, System Software: An Introduction to Systems Programming (3rd), Addison-Wesley, 1997.
The ISA Level The Instruction Set Architecture (ISA) is positioned between the microarchtecture level and the operating system level.  Historically, this.
Computer Architecture
Computer Science 210 Computer Organization The Instruction Execution Cycle.
CPS120: Introduction to Computer Science
MIPS coding. SPIM Some links can be found such as:
Computer Systems Organization CS 1428 Foundations of Computer Science.
The ISA Level The Instruction Set Architecture (ISA) is positioned between the microarchtecture level and the operating system level.  Historically, this.
Chapter 1 Computer architecture Languages: machine, assembly, high
April 23, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 9: Assemblers, Linkers, and Loaders * Jeremy R. Johnson Mon. April 23,
Computer Operations A computer is a programmable electronic device that can store, retrieve, and process data Data and instructions to manipulate the data.
Chapter 7 Low-Level Programming Languages. 2 Chapter Goals List the operations that a computer can perform Discuss the relationship between levels of.
Chapter 7 Low-Level Programming Languages (slides modified by Erin Chambers)
Chapter 7 Low-Level Programming Languages Nell Dale John Lewis.
The Instruction Set Architecture. Hardware – Software boundary Java Program C Program Ada Program Compiler Instruction Set Architecture Microcode Hardware.
Branch Addressing op rs rt address address beq $s1, $s2, Label if ($s1 = =$s2) go to Label 6 bits 5 bits 5 bits 16 bits effective 32 bit address.
Computer Operation. Binary Codes CPU operates in binary codes Representation of values in binary codes Instructions to CPU in binary codes Addresses in.
CC410: System Programming Dr. Manal Helal – Fall 2014 – Lecture 10 – Loaders.
CPS4200 System Programming Spring 1 Systems Programming Chapter 1 Background I.
國立政治大學資訊科學系 Introduction
김길용 교수 분산처리연구실 시스템 프로그래밍 김길용 교수 분산처리연구실
Programmable System on Chip
MIPS Instruction Set Advantages
Prof . Ki-Dong Chung Pusan Nat’l University
System Programming and administration
System Programming and administration
System Programming Design and Implementation of system software.
ACOE301: Computer Architecture II Labs
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
THE sic mACHINE CSCI/CMPE 3334 David Egle.
CSCE Fall 2013 Prof. Jennifer L. Welch.
Simplified Instructional Computer (SIC)
Chapter 1 Background Professor Gwan-Hwan Hwang
Simplified Instructional Computer (SIC)
ultraSPARC과 SIC/XE Machine 비교
CSCE Fall 2012 Prof. Jennifer L. Welch.
Under Address Modes Source: under
CPU has 6 special locations called registers
Welcome to Systems Software
Chapter 4: Computer Architecture
Chapter 1 Computer architecture Languages: machine, assembly, high
SYSTEM SOFTWARE CS2304 Dr.A.KANNAN, PROFESSOR & HEAD,
System Programming By Prof.Naveed Zishan.
Lecture 1: SIC Architecture
Presentation transcript:

系 統 程 式 System Programming

BACKGROUND 1/3 1. What is system software ? 2. Major topics about system software: Assemblers, Loader and Linkers, macroprocessors, compilers operating systems, database management systems, text editors, interactive debugging systems. 3. What is the difference between AP and SP ? It is machine dependency.

BACKGROUND 2/3 4. Each system software is described by the following functions: fundamental features machine-independent features machine-dependent features Major design idea Example of implementations

BACKGROUND 3/3 5. Simplified Instructional Computer (SIC), SIC/XE (with extra equipment) (1)memory (2)registers (3)data formats (4)Instruction formats (5)addressing mode

SIC machine architecture 1/2 (1)Memory 8-bit byte, 24-bit word, 32k memory size(=215) (2)Instruction format 8 1 15 (3)Data format Integer: 24-bit binary numbers (2’s complement for negative). Character: 8-bit ASCII codes. opcode x address

SIC machine architecture 2/2 (4)Addressing mode Direct : X=0, target address = address Indexed : X=1, target address = address +(X) (5)Register A: accumulator X: index register L: linkage register PC : program counter SW : status word

SIC/XE machine architecture 1/5 (1)Memery 1 M memory Size (=220) (2)Instruction format 8 8 4 4 6 1 1 1 1 1 1 12 6 1 1 1 1 1 1 20 opcode opccode register opcode n i x b p e displacement opcode n i x b p e displacement

SIC/XE machine architecture 2/5 (3)Data format Floatng-point : 1 11 36 s exponent fraction

SIC/XE machine architecture 3/5 (4)Addressing mode Program-counter relative : b=0, p=1, TA=(PC) + disp (-2048<=disp<=2047) Base relative : b=1, p=0, TA=(B) + disp (0<=disp<=4095) Direct : i=0, n=0, TA=(disp or addr) Index : X=1

SIC/XE machine architecture 4/5 Immediate : i=1, n=0, operand=disp Indirect : i=0, n=1, TA’=(TA) Extended : i=1, n=1, e=1, TA=addr

SIC/XE machine architecture 5/5 (5)Register B : base register S : general working register T : general working register F : floating-point accumulator (48-bit)

CPU Memory I / O PC IR Decoder ALU CU ACC ( P C ) instruction Data (LDA) Decoder ( T A ) Data

LDA

Hex: 0 3 2 6 0 0 Machine instruction Hex Binary op n i x b p e disp/address (1)032600 000000 1 1 0 0 1 0 0110 0000 0000 LDA:load address SIC/XE pc:program counter Target address : 003000(program counter)+ 6 0 0 = 3 6 0 0 Value loaded into register A: 103000 · · p11. figure(a) : 3600 103000 000000 110010 0110 0000 0000 · · Hex: 0 3 2 6 0 0

Hex: 0 3 C 3 0 0 Hex op n i x b p e disp/address LDA:load address SIC/XE index base Target address : 000090(index register) + 3 0 0 006000(base register) = 6 3 9 0 Value loaded into register A: 00C303 · · · · p11. figure(a) : 6390 00C303 000000 111100 0011 0000 0000 · · Hex: 0 3 C 3 0 0

Hex: 0 2 2 0 3 0 Hex op n i x b p e disp/address (3)022030 000000 1 0 0 0 1 0 0000 0011 0000 indirect pc Target address : 003000(program counter) + 0 3 0 = 3 0 3 0 (indirect address) load address:3 6 0 0 · · Value loaded into register A: 103000 3030 003600 · · p11. figure(a) : · · 3600 103000 000000 100010 0000 0011 0000 · · Hex: 0 2 2 0 3 0

Hex op n i x b p e disp/address (4)010030 000000 0 1 0 0 0 0 0000 0011 0000 immediate Target address : + 0 3 0 = 3 0 Value loaded into register A: 000030 000000 010000 0000 0011 0000 Hex : 0 1 0 0 3 0

Hex: 0 0 3 6 0 0 Hex op n i x b p e disp/address (5)003600 000000 0 0 0 0 1 1 0110 0000 0000 SIC(direct) Target address : (direct address) 3 6 0 0 Value loaded into register A: 103000 · · p11. figure(a) : 3600 103000 000000 000011 0110 0000 0000 Hex: 0 0 3 6 0 0

Hex:0 3 1 0 C 3 0 3 (6) Hex op n i x b p e disp/address SIC/XE extended Target address : 0 C 3 0 3 Value loaded into register A: 003030 · · · · p11. figure(a) : C303 003030 000000 110001 0000 1100 0011 0000 0011 Hex:0 3 1 0 C 3 0 3

Sample data movement operations for (a)SIC and (b)SIC/XE LDA FIVE STA ALPHA LDCH CHARZ STCH C1 . ALPHA RESW 1 FIVE WORD 5 CHARZ BYTE C ’ Z ’ C1 RESB 1 LDA # 5 STA ALPHA LDA # 90 STCH C1 C1 RESB 1

Sample data movement operations for (a)SIC CPU A: (ACC) MEMORY (word) FIVE: ALPHA: (byte) CHARZ: C1: (Z:character) 5 Z 5 5 Z Z LDA FIVE STA ALPHA LDCH CHARZ STCH C1 . ALPHA RESW 1 FIVE WORD 5 CHARZ BYTE C ’ Z ’ C1 RESB 1

Sample data movement operations for (b)SIC/XE CPU A: (ACC) MEMORY (word) ALPHA: (byte) C1: 5 90 5 90->5A (ASCII CODE) =Z LDA # 5 STA ALPHA LDA # 90 STCH C1 . ALPHA RESW 1 C1 RESB 1

Sample arithmetic operations for (a)SIC and (b)SIC/XE LDA ALPHA ADD INCR SUB ONE STA BETA BETA←ALPHA+INCR-ONE LDA GAMMA STA DELTA DELTA←GAMMA+INCR-ONE . ONE WORD 1 ALPHA RESW 1 BETA RESW 1 GAMMA RESW 1 DELTA RESW 1 INCR RESW 1 1/2

Sample arithmetic operations for (a)SIC and (b)SIC/XE LDS INCR LDA ALPHA ADDR S , A SUB # 1 STA BETA LDA GAMMA ADDR S , A STA DELTA . ALPHA RESW 1 BETA RESW 1 GAMMA RESW 1 DELTA RESW 1 INCR RESW 1 2/2

Sample looping and indexing operation for (a)SIC,(b)SIC/XE LDX ZERO MOVECH LDCH STR1 , X STCH STR2 , X TIX ELEVEN JLT MOVECH . STR1 BYTE C ‘ TEST STRING ‘ STR2 RESB 11 ZERO WORD 0 ELEVEN WORD 11 (a) 1/2

Sample looping and indexing operations for (a)SIC CPU X: PC ACC Status word: MEMORY (word) ZERO: ELEVEN: (byte) STR1: STR2: 0 ->1 ( test X=1 ,ELEVEN=11 ) ( 1 < 11 ) MOVECH 11 T T E S T S T R I N G < T LDX ZERO MOVECH LDCH STR1 , X STCH STR2 , X TIX ELEVEN JLT MOVECH . STR1 BYTE C ’ TEST STRING ‘ STR2 RESB 11 . ZERO WORD 0 ELEVEN WORD 11

Sample looping and indexing operation for (a)SIC,(b)SIC/XE LDT # 11 LDX # 0 MOVECH LDCH STR1 , X STCH STR2 , X TIXR T JLT MOVECH . STR1 BYTE C ’ TEST STRING ‘ STR2 RESB 11 (b) 2/2

Sample looping and indexing operations for (b)SIC/XE CPU X: T: PC ACC Status word: MEMORY (byte) STR1: STR2: 0 ->1 ( text X=1 ,T= 11 ) ( 1 < 11 ) 11 MOVECH T T E S T S T R I N G < T LDT #11 LDX #0 MOVECH LDCH STR1 , X STCH STR2 , X TIXR T JLT MOVECH . STR1 BYTE C ’ TEST STRING ‘ STR2 RESB 11

Sample indexing and looping operation for (a)SIC,(b)SIC/XE LDA ZERO STA INDEX ADDLP LDX INDEX LDA ALPHA , X ADD BETA , X STA GAMMA , X LDA INDEX ADD THREE STA INDEX COMP K300 JLT ADDLP . INDEX RESW 1 ALPHA RESW 100 BETA RESW 100 GAMMA RESW 100 ZERO WORD 0 K300 WORD 300 1/2 (a)

Sample indexing and looping operation for (a)SIC,(b)SIC/XE LDS # 3 LDT # 300 LDX # 0 ADDLP LDA ALPHA , X ADD BETA, X STA GAMMA, X ADDR S , X COMPR X , T JLT ADDLP . ALPHA RESW 100 BETA RESW 100 GAMMA RESW 100 (b) 2/2

Sample input and output operations for SIC INLOOP TD INDEV JEQ INLOOP RD INDEV ACC←INPUT STCH DATA ACC→DATA . OUTLP TD OUTDEV JEQ OUTLP LDCH DATA ACC←DATA WD OUTDEV ACC→OUTPUT INDEV BYTE X ‘ F1 ‘ OUTDEV BYTE X ‘ 05 ‘ DATA RESB 1 pooling busy waiting

Sample subroutine call and record input operations for(a)SIC (b) SIC/XE JSUB READ . READ LDX ZERO RLOOP TD INDEV JEQ RLOOP RD INDEV STCH RECORD , X TIX K100 JLT RLOOP RSUB INDEV BYTE X ‘ F1 ‘ RECORD RESB 100 ZERO WORD 0 K100 WORD 100 (a) 1/2 RECORD … X=1 =2 … 100

Sample subroutine call and record input operations for(a)SIC (b) SIC/XE JSUB READ . READ LDX # 0 LDT # 100 RLOOP TD INDEV JEQ RLOOP STCH RECORD , X TIXR T JLT RLOOP RSUB INDEV BYTE X ’ F1 ‘ RECORD RESB 100 (b) 2/2