FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n Logic synthesis. n Placement and routing.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Logic optimization n Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library. n Optimization goals: minimize area, meet delay constraint; some power optimizations.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Syntax-directed translation n Translate HDL into logic directly. –ab + ac n Generally requires optimization.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Macros n Pre-designed logic. –Generally identified by language features. –+ operator. –xxx() n Hard macro: includes placement. n Soft macro: no placement.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Logic synthesis phases n Technology-independent optimizations work on logic representations that do not directly model logic gates. n Technology-dependent optimizations work in the available set of logic gates. n Transformation from technology- independent to technology-dependent is called library binding.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Technology-independent optimizations n Works on Boolean expression equivalent. n Estimates size based on number of literals. n Uses factorization, resubstitution, minimization, etc. to optimize logic. n Technology-independent phase uses simple delay models.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Technology-dependent optimizations n Maps Boolean expressions into a particular cell library. n Mapping may take into account area, delay. n May perform some optimizations on addition to simple mapping. n Allows more accurate delay models.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Boolean network n A Boolean network is the main representation of the logic functions for technology independent optimizations. n Each node can be represented as sum-of- products (or product-of-sums). n Provides multi-level structure, but functions in the network need not correspond to logic gates.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Boolean network example out1 = k2 + x2’out2 = k3 + x1 k2 = x1’ x2 x4 + k1 k3 = k1 x4’ k1 = x2 + x3 x1 x2x3x4 primary outputs primary inputs

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Terms n Support: set of variables used by a function. n Transitive fanout: all the primary outputs and intermediate variables of a function. n Transitive fanin: all the primary inputs and intermediate variables used by a function. Transistive fanin determines a cone of logic. cone primary inputs output

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Technology-independent logic optimization n Simplification rewrites node to simplify its form. n Network restructuring introduces new nodes for common factors, collapses several nodes into one new node. n Delay restructuring changes factorization to reduce path length.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Cost in the Boolean network n Don’t know exact gate structure, but can estimate final network cost: –area estimated by number of literals (true or complement forms of variables); –delay estimated by path length.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Partially-specified functions n Don’t-cares can be implemented in either the on-set or off-set. n Don’t-cares provide the greatest opportunities for minimization in many cases.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Partially-specified function example x1x1 x2x2 x3x don’t care

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Don’t-cares in Boolean networks n In two-level function, don’t-cares are defined at primary output. n In Boolean network, structure of network itself introduces don’t-cares. n Types of structural don’t-cares: –satisfiability; –observability.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Satisfiability don’t-cares n Occur when an intermediate variable value is inconsistent with its function inputs. Since this can’t happen, we don’t care. g=ab f=yc abc y y == g a=b=0, f=1 can’t happen Don’t-care for f: y’g + yg’

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Observability don’t-cares n Occur when an intermediate variable’s value doesn’t affect the network primary outputs. a b x If a=1, then b is don’t-care

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Optimizations n Simplification. –Changing the way a function is represented. n Network restructuring. –Adding and removing nodes. n Delay restructuring. –Optimizations that reduce the height of critical paths.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Cube representation n On-set, off-set, don’t-care set, cover: x1 x2 x3

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Espresso example x1 x2 x3

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Partial collapsing beforeafter f1 f2f3 f4F f3 f4

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Factorization n Based on division: –formulate candidate divisor; –test how it divides into the function; –if g = f/c, we can use c as an intermediate function for f. n Algebraic division: don’t take into account Boolean simplification. Less expensive then Boolean division.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Factorization using division n Three steps: –generate potential common factors and compute literal savings if used; –choose factors to substitute into network; –restructure the network to use the new factors. n Algebraic/Boolean divison can be used to implement first step.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Technology mapping n Cover the function:

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR FPGA tech mapping n Cost (number of inputs) doesn’t always increase with added functions:

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR FPGAs vs. custom logic n Cost metric for static gates is literal: –ax + bx’ has four literals, requires 8 transistors. n Cost metric for FPGAs is logic element: –All functions that fit in an LE have the same cost.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR LUT-based logic synthesis n Find the largest logic cone that will fit into the LUT: r = q + s’ q = g’ + h s = d’ d = a + b

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Placement and routing n Two critical phases of layout design: –placement of components on the chip; –routing of wires between components. n Placement and routing interact, but separating layout design into phases helps us understand the problem and find good solutions.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Placement metrics n Quality metrics for layout: –area; –delay. n Area and delay determined partly by wiring. n How do we judge a placement without wiring? Estimate wire length without actually performing routing. n Design time may be important for FPGAs

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wire length as a quality metric bad placementgood placement

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wire length measures n Estimate wire length by distance between components. n Possible distance measures: –Euclidean distance (sqrt(x 2 + y 2 )); –Manhattan distance (x + y). n Multi-point nets must be broken up into trees for good estimates. Euclidean Manhattan

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wiring trees Steiner point

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Placement techniques n Can construct an initial solution, improve an existing solution. n Pairwise interchange is a simple improvement metric: –Interchange a pair, keep the swap if it helps wire length. –Heuristic determines which two components to swap.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Placement by partitioning n Works well for components of fairly uniform size. n Partition netlist to minimize total wire length using min-cut criterion. n Partitioning may be interpreted as 1-D or 2- D layout.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Recursive partitioning

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Min-cut bisecting partitioning partition 1partition 2 A B C D 3 nets 1 net

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Min-cut bisecting partitioning, cont’d n Swapping A and B: –B drags 1 net; –A drags 3 nets; –total cut increase: 3 nets. n Conclusion: probably not a good swap, but must be compared with other pairs.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Kernighan-Lin algorithm n Compute min cut criterion: –count total net cut change. n Algorithm exchanges sets of nodes to perform hill-climbing—finding improvements where no single swap will improve the cut. n Recursively subdivide to determine placement detail.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Simulated annealing n Powerful but CPU-intensive optimization technique. n Analogy to annealing of metals: –temperature determines probability of a component jumping position; –probabilistically accept moves. –start at high temperature, cool to lower temperature to try to reach good placement.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Routing n Major phases in routing: –global routing assigns nets to routing areas; –detailed routing designs the routing areas. n Net ordering is a major problem. Order in whch nets are routed determines quality fo result. Net ordering is a heuristic.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Global routing n Choose a sequence of channels. –Not tracks within a channel. n Must take capacity into account. n Channel graph allows path algorithms to be used for global routing.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Channel graph LE channel switch box switch box switch box switch box switch box switch box switch box switch box switch box

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Maze routing n Will find shortest path for a single wire, if such a path exists. n Two phases: –Label nodes with distance, radiating from source. –Use distances to trace from sink to source, choosing a path that always decreases distance to source.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Lee (wavefront) router

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR FPGA issues n Often want a fast answer. May be willing to accept lower quality result for less place/route time. n May be interested in knowing wirability without needing the final configuration. n Fast placement: constructive placement, iterative improvement through simulated annealing.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR FPGA routing n Finding a route into given interconnection network. n Global routing assigns to channels. n Local routing selects the programming points used to make the connections.

FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR FPGA routing techniques n Nair: route based on congestion, not distance. Route in two passes: –Estimate congestion. –Final routing. n Triptych: more gradual penalty for congestion.