Processor Design Computer Architecture CS 215

CPU Design  Control Unit Generates the control signals in the correct order to effect the correct data path activity  Data Path Set of interconnections and auxiliary registers Needed to accomplish overall changes an instruction makes CPU Control Unit Data Path Control signals out Control unit inputs

1-Bus Microarchitecture

Abstract Vs. Concrete RTN How would accomplish the following instruction using this architecture? add(:=op=12)  R[ra]  R[rb]+R[rc]:

Abstract Vs. Concrete RTN add(:=op=12)  R[ra]  R[rb]+ R[rc]: StepRTN

Abstract Vs. Concrete RTN: addi StepRTN T0.MA  PC: C  PC + 4; T1.MD  M[MA]; PC  C; T2.IR  MD; T3.A  R[rb]; T4.C  A + c2 {sign ext.}; T5.R[ra]  C;

Abstract Vs. Concrete RTN: ld StepRTN T0-T2 Instruction fetch T3.A  (rb=0  0: rb  0  R[rb]); T4.C  A + #IR ); T5.MA  C; T6.MD  M[MA]; T7.R[ra]  MD;

Abstract Vs. Concrete RTN: st StepRTN T0-T2 Instruction fetch T3.A  (rb=0  0: rb  0  R[rb]); T4.C  A + #IR ); T5.MA  C; T6.MD  R[ra]; T7.M[MA]  MD;

Abstract Vs. Concrete RTN: br StepRTN T0-T2 Instruction fetch T3.CON  cond(R[rc]); T4.CON  PC  R[rb];

Abstract Vs. Concrete RTN: shr StepConcrete RTN T0-T2 Instruction fetch T3.n  IR ; T4.(n=0)  (n  R[rc] ; T5.C  R[rb]; T6.Shr (:= (n≠0)  (C  0#C : n  n-1; Shr) ); T7.R[ra]  C;

More Detail …

ra, rb, rc fields General purpose registers Control signals 5x32 decoder

Try this!  Problem Extend the SRC instruction set by adding the XOR command (op=19), similar to the AND command Note: The ALU cannot be altered by adding XOR Develop both an abstract and concrete RTN for the instruction

Instruction Register

Memory Interface

ALU

Control sequences: Instruction Fetch StepConcrete RTNControl Sequence T0.MA  PC: C  PC+4;PC out, MA in, Inc4, C in T1.MD  M[MA]: PC  C;Read, C out, PC in, Wait T2.IR  MD;MD out, IR in T3.Instruction_execution

Control sequences: add StepConcrete RTNControl Sequence T0.MA  PC: C  PC+4;PC out, MA in, Inc4, C in, Read T1.MD  M[MA]: PC  C;C out, PC in, Wait T2.IR  MD;MD out, IR in T3.A  R[rb];Grb, R out, A in T4.C  A + R[rc];Grc, R out, ADD, C in T5.R[ra]  C;C out, Gra, R in, End

Control sequences: addi StepConcrete RTNControl Sequence T0.MA  PC: C  PC + 4; PC out, MA in, Inc4, C in T1.MD  M[MA]; PC  C;C out, PC in, Wait, Read T2.IR  MD;MD out, IR in T3.A  R[rb];Grb, R out, A in T4.C  A + c2   {sign ext.};c2 out, ADD, C in T5.R[ra]  C;C out, Gra, R in, End

Control sequences: st StepConcrete RTNControl Sequence T0-T2Instruction fetch Instruction fetch T3.A  (rb=0)  0: rb  0  R[rb];Grb, BA out, A in T4.C  A + c2   {sign ext.};c2 out, ADD, C in T5.MA  C;C out, MA in T6.MD  R[ra];Gra, R out, MD in, Write T7.M[MA]  MD;Wait, End } address arithmetic

Control sequences: shr StepConcrete RTNControl Sequence T0-T2Instruction fetchInstruction fetch T3.n  IR  4..0  ;c1 out, Ld T4.(n=0)  (n  R[rc]  4..0  );n=0  (Grc, R out, Ld) T5.C  R[rb];Grb, R out, C=B, C in T6.Shr (:=(n≠0)  n  0  (C out, SHR, C in, (C    0#C   :Decr, Goto6) n  n-1; Shr) ); T7.R[ra]  C;C out, Gra, R in, End

Control sequences: br StepConcrete RTNControl Sequence T0-T2Instruction fetchInstruction fetch T3.CON  cond(R[rc]);Grc, R out, CON in T4.CON  PC  R[rb];Grb, R out, CON  PC in, End

Clocking & Timing

Control Unit

2-Bus SRC

3-Bus SRC

Machine Reset  From a need to initialize processor to a known, defined state Control Step Counter  0 PC  Known Value  RTN instruction_interpretation := (  Run  Strt  (Run  1: PC, R[0..31]  0); Run  Rst (IR  M[PC]: PC  PC + 4; instruction_execution): Run  Rst  ( Rst  0: PC  0); instruction_interpretation):

Types of Exceptions  System Reset  Machine Check Exceptions Memory error checking  Data Access Exceptions  Instruction Access Exceptions  Alignment Exceptions

Types of Exceptions  Program Exceptions Illegal instruction Unimplemented instruction Privileged instruction Arithmetic errors (sometimes)

Types of Exceptions  Miscellaneous Hardware Exceptions Countdown to zero  Trace & Debugging Exceptions  Nonmaskable Exceptions Cannot be ignored Power outage  Interrupts (External)

Exception Process  Interrupt signal asserted  Determine if interrupt should be serviced; Finish current instruction, if possible

Exception Process instruction_interpretation := (  Run  Strt  Run  1: Run  (ireq  IE)  (IR  M[PC]: PC  PC + 4; instruction_execution): Run  (ireq  IE)  (IPC  PC   : II    Isrc_info   : iack  1: IE  0: PC  Ivect   ; iack  0); instruction_interpretation);