Chapter 4 -- Modular Combinational Logic

Decoders

Decoder Realization

More complex decoders

Example Realize f(Q,X,P) =  m(0,1,4,6,7) =  M(2,3,5)

Example 4.1 (concluded)

SN Decoder Module

Four-to-one multiplexer design

Use a 74151A multiplexer to Realize f(x 1,x 2,x 3 ) =  m(0,2,3,5) Figure 4.30

Half Adders Figure 4.35 (a) -- (c)

Full Adders Figure 4.35 (d) -- (g)

Ripple Carry Adder Figure 4.36

Addition Time for a Basic Ripple-Carry Adder Let t gate = the propogation delay through a typical logic gate Half adder propagation delays t add = 3 t gate t carry = 2 t gate Full adder propagation delays t add = 3 t gate t carry = 2 t gate Ripple-Carry Adder (n-bits) t add = (n - 1)2 t gate + 3 t gate = (2n + 1) t gate

SN7482 Two-Bit Pseudo Parallel Adder Module Package Pin Configuration

SN7482 Pseudo Parallel Adder -- Truth Table

SN7482 Pseudo Parallel Adder -- Logic Diagram

SN7482 Two-Bit Adder -- Logic Equations C1 = C0A1 + C0B1 + A1B1(4.20)  1 = C0C1 + A1C1 + B1C1 + A1B1C0 = C1(C0 + A1 + B1) + A1B1C0 = (C0+A1)(C0+B1)(A1+B1) (C0 +A1+B1) +A1B1C0 = (C0+ A1B1)(A1+B1)(C0 +A1+B1) +A1B1C0(4.21) = [C0(A1+B1)+ C0A1B1](A1+B1)+A1B1C0 = C0A1B1+C0A1B1+C0A1B1+A1B1C0 = C0  A1  B1 Similarly C2 = C1A2 + C1B2 + A2B2(4.22)  2 = C1  A2  B2

Add Time for SN7482 Adder Circuits SN7482 propagation delays t  1 = 5 t gate t C1 = 2 t gate t  2 = 6 t gate t C2 = 4 t gate SN7482-based ripple-carry adder (n-bits) t add = (2n + 2) t gate

SN7483 Four-Bit Adder Module Package Pin Configuration

SN7483 Four-Bit Adder Module -- Logic Diagram

SN7483 Four-Bit Adder -- Logic Equations Pi = (BiAi)(Ai + Bi) = (Ai + Bi)(Ai + Bi) = Ai  Bi (4.24)  i = Pi  Ci-1 = Ai  Bi  Ci-1 (4.25) C1 = [C0(A1B1) + (A1 + B1)] = [C0(A1B1)](A1 + B1) = (C0+(A1B1))(A1 + B1) = C0A1 + C0B1 + A1B1 (4.26) Similarly Ci = Ci-1Ai + Ci-1Bi + AiBi

Add Times for SN7483 Adder Circuits SN7483 propagation delays t  1 = 3 t gate t  2 = t  3 = t  4 = 4 t gate t C1 = t C2 = t C3 = t C4 = 3 t gate SN7483-based Ripple-Carry Adder (n-bits) t add = (3m + 1) t gate where m =  n/4 .

Fully Parallel Three-Bit Adder c 0 = x 0 y 0 (4.30) s 0 = x 0  y 0 c 1 = x 1 y 1 c 0 ’+x 1 y 1 c 0 +x 1 y 1 ’c 0 +x 1 ’y 1 c 0 = x 1 y 1 +(x 1  y 1 )c 0 = x 1 y 1 +(x 1  y 1 )(x 0 y 0 ) (4.31) s 1 = x 1  y 1  c 0 = x 1  y 1  x 0 y 0 c 2 = x 2 y 2 +(x 2  y 2 )c 1 = x 2 y 2 +(x 2  y 2 )[x 1 y 1 +(x 1  y 1 )(x 0 y 0 )] = x 2 y 2 +(x 2  y 2 )(x 1 y 1 )+(x 2  y 2 )(x 1  y 1 )(x 0 y 0 ) (4.32) s 2 = x 2  y 2  c 1 = x 2  y 2  [x 1 y 1 +(x 1  y 1 )(x 0 y 0 )]

Add Time for a Fully Parallel Adder Assuming a three-level realization t add = 3 t gate However, the fan in requirements become impractical as n increases.

Carry Look-Ahead Adders -- Basic Idea Recall that c i = x i y i + x i c i-1 + y i c i-1 = x i y i + x i y i c i-1 + x i y i c i-1 + x i y i c i-1 + x i y i c i-1 = x i y i + x i y i c i-1 + x i y i c i-1 = x i y i + (x i y i + x i y i )c i-1 = x i y i + (x i  y i )c i-1 Letg i = x i y i [carry generate](4.33) p i = x i  y i [carry propagate](4.34) Thenc i = g i + p i c i-1 s i = p i  c i-1 (4.38)

Carry Look-Ahead Adders -- Three-Bit Example c 0 = g 0 (4.35) s 0 = p 0 c 1 = g 1 + p 1 c 0 = g 1 + p 1 g 0 (4.36) s 1 = p 1  c 0 c 2 = g 2 + p 2 c 1 = g 2 + p 2 (g 1 + p 1 g 0 ) = g 2 + p 2 g 1 + p 2 p 1 g 0 (4.37) s 2 = p 2  c 1

Carry Look-Ahead Adder Design (c) Figure 4.39

Add Times for Carry Look-Ahead Adders Adder modules t g = t p = t s = t gate CLA module t c = 2 t gate Overall t add = t gate + 2 t gate + t gate = 4 t gate

Binary Subtraction Circuits Recall that(R) 2 = (P) 2 - (Q) 2 = (P) 2 + (-Q) 2 = (P) 2 + [Q] 2 = (P) 2 + (Q) For an SN7483 adder (  ) 2 = (A) 2 + (B) 2 + (C0) 2 (4.39) where  =  4  3  2  1, A = A4A3A2A1, and B = B4B3B2B1 If C0 = 0, A = P, and B = Q, then (  ) 2 = (P) 2 + (Q) 2. If C0 = 1, A = P, and B = Q, then (  ) 2 = (P) 2 - (Q) 2.

Two’s Complement Adder/Subtracter Figure 4.41

Arithmetic Overflow Detection a n-1 b n-1 c n-2 c n-1 s n-1 V

Overflow Detection Circuits Figure 4.42