© S. Ramesh / Kavi Arya / Krithi Ramamritham IT-606 Embedded Systems (Software) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay.

Slides:



Advertisements
Similar presentations
© S. Ramesh / Kavi Arya / Krithi Ramamritham 1 IT-606 Embedded Systems (Software ) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay.
Advertisements

While Loops and If-Else Structures
COMMUNICATING SEQUENTIAL PROCESSES C. A. R. Hoare The Queen’s University Belfast, North Ireland.
Models of Concurrency Manna, Pnueli.
Combinational Logic.
Ch 7 B.
The cardiac pacemaker – SystemJ versus Safety Critical Java Heejong Park, Avinash Malik, Muhammad Nadeem, and Zoran Salcic. University of Auckland, NZ.
The Synchronous Model of Computation Stavros Tripakis UC Berkeley EE 249 Lecture – Sep 15, 2009 CE 290I Lecture – Oct 22, 2009.
Process Synchronization. Module 6: Process Synchronization Background The Critical-Section Problem Peterson’s Solution Synchronization Hardware Semaphores.
While Loops. Challenge: ● Ask the user a simple math questions ● Continue asking the question until the user gets it right.
Optimized State Encoding for Esterel Programs Dumitru POTOP-BUTUCARU.
Copyright © 2001 Stephen A. Edwards All rights reserved The Synchronous Language Esterel Prof. Stephen A. Edwards.
5 Mar 001animation check Animation check for on-line presentations Ellen M. Sentovich.
Weakly endochronous systems Dumitru Potop-Butucaru IRISA, France Joint work with A. Benveniste and B. Caillaud.
© S. Ramesh / Kavi Arya / Krithi Ramamritham 1 IT-606 Embedded Systems (Software ) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay.
Ladder Logic PLC Programs are made up of combinations of AND; OR; NAND; NOR; and other gates, along with timers, inputs, outputs, counters, comparators,
Implementing Constructive Synchronous Programs on POLIS CFSM Networks G.Berry E.Sentovich Ecole des Mines de Paris / INRIA Cadence Berkeley Labs.
Esterel Overview Roberto Passerone ee249 discussion section.
Sources Gang Quan Univ. of Notre Dame Finite State Machines.
Mahapatra-A&M-Sprong'021 Co-design Finite State Machines Many slides of this lecture are borrowed from Margarida Jacome.
Einsterel: A Compiled Event-Driven Simulator for Esterel.
Chapter 6 Control Statements Continued
Administrative MUST GO TO CORRECT LAB SECTION! Homework due 11:59pm on Tuesday. 25 points off if late (up to 24 hours) Cannot submit after 11:59pm on Wednesday.
A Mystery Esterel –small no type inference, subtyping, … no recursion, functions, … no pointers, malloc, GC, … no complex data structures, libraries,
Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.
Programming & Scratch. Programming Learning to program is ultimately about learning to think logically and to approach problems methodically. The building.
1 Levi Lúcio © A Test Selection Language for CO-OPN Specifications Levi Lúcio, Luis Pedro and Didier Buchs University of Geneva.
An introduction to Esterel and its compilation
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
“Software” Esterel Execution (work in progress) Dumitru POTOP-BUTUCARU Ecole des Mines de Paris
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
Mahapatra-A&M-Fall'001 Co-design Finite State Machines Many slides of this lecture are borrowed from Margarida Jacome.
Sources Gang Quan Univ. of Notre Dame Finite State Machines.
Control Structures Repetition or Iteration or Looping Part II.
© S. Ramesh / Kavi Arya / Krithi Ramamritham 1 IT-606 Embedded Systems (Software) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay.
© S. Ramesh / Krithi Ramamritham / Kavi Arya 1 IT-606 Embedded Systems (Software) S. Ramesh Krithi Ramamritham Kavi Arya KReSIT/ IIT Bombay.
Behavioral Modelling - 1. Verilog Behavioral Modelling Behavioral Models represent functionality of the digital hardware. It describes how the circuit.
© S. Ramesh / Kavi Arya / Krithi Ramamritham 1 IT-606 Embedded Systems (Software ) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay.
Chapter 6 Control Statements Continued
CSC 107 – Programming For Science. Today’s Goal  Know how to use and write for loops  Explain why to use for, while, & do-while loops  Convert between.
While and If-Else Loops ROBOTC Software. While Loops While loop is a structure within ROBOTC Allows a section of code to be repeated as long as a certain.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
Introduction to Verilog. Data Types A wire specifies a combinational signal. – Think of it as an actual wire. A reg (register) holds a value. – A reg.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Conditionals Conditional statements, called conditionals for short, are statements in the if-then or if-then-else form. Examples: “If the alarm goes off,
55:032 - Intro. to Digital DesignPage 1 VHDL and Processes Defining Sequential Circuit Behavior.
CSCI1600: Embedded and Real Time Software Lecture 15: Advanced Programming Concepts Steven Reiss, Fall 2015.
Introduction to Verilog. Structure of a Verilog Program A Verilog program is structured as a set of modules, which may represent anything from a collection.
Design by Contract. The Goal Ensure the correctness of our software (correctness) Recover when it is not correct anyway (robustness) Correctness: Assertions.
Concurrency/synchronization using UML state models November 27th, 2007 Michigan State University.
Secure Information Flow for Reactive Programming Paradigm Zhengqin Luo SAFA workshop 2009.
Sensor Information: while loops and Boolean Logic.
CIS3931 – Intro to JAVA Lecture Note Set 2 17-May-05.
Programming & Scratch.
Clocks A clock is a free-running signal with a cycle time.
Esterel By: Sam Weinberg.
Using the Stopwatch object
Chapter 4 LOOPS © Bobby Hoggard, Department of Computer Science, East Carolina University / These slides may not be used or duplicated without permission.
DESICION TABLE Decision tables are precise and compact way to model complicated logic. Decision table is useful when input and output data can be.
While Loops and If-Else Structures
While Loops and If-Else Structures
While Loops and If-Else Structures
While Loops and If-Else Structures
if-else Structures Principles of Engineering
Sequential Logic.
Lecture 5 Binary Operation Boolean Logic. Binary Operations Addition Subtraction Multiplication Division.
While Loops and If-Else Structures
Esterel Tutorial Winter 2004
While Loops and If-Else Structures
While Loops And If-Else Structures
Presentation transcript:

© S. Ramesh / Kavi Arya / Krithi Ramamritham IT-606 Embedded Systems (Software) S. Ramesh Kavi Arya Krithi Ramamritham KReSIT/ IIT Bombay

© S. Ramesh / Kavi Arya / Krithi Ramamritham Esterel: Advanced Features S. Ramesh

© S. Ramesh / Kavi Arya / Krithi Ramamritham Multiform notion of time Belt Controller Specification: " Five seconds after the key is turned on, if the belt has not been fastened, an alarm will beep for five seconds or until the key is turned off"

© S. Ramesh / Kavi Arya / Krithi Ramamritham Declaration module belt_control: input reset, key_on, key_off, belt_on, end_5, end_10; output alarm(boolean), start_timer;

© S. Ramesh / Kavi Arya / Krithi Ramamritham Module body loop abort emit alarm(false); every key_on do abort emit start_timer; await end_5; emit alarm(true); await end_10; when [key_off or belt_on]; emit alarm(false); end when reset end

© S. Ramesh / Kavi Arya / Krithi Ramamritham module timer : constant count_5 : integer ; input msec, start_timer ; output end_5, end_10 ; every start_timer do await count_5 msec ; emit end_5 ; await count_5 msec ; emit end_10 ; end.

© S. Ramesh / Kavi Arya / Krithi Ramamritham Instantaneous dialogue module inst_dialogue: input I; output S; signal Q, Y in [ await tick; present I then emit Q end; present Y then emit S end  every Q do emit Y end ] end module

© S. Ramesh / Kavi Arya / Krithi Ramamritham Input I triggers local Q Q triggers Y Y triggers S all happen instantaneously in the same reaction

© S. Ramesh / Kavi Arya / Krithi Ramamritham Another example P: [ emit are_u_ready; present I_am_ready then emit success; stat1 else emit fail; stat2 ]

© S. Ramesh / Kavi Arya / Krithi Ramamritham Q: loop do [ loop emit I_am_ready; each are_u_ready || stat3; ]; upto change; do stat4 upto change end

© S. Ramesh / Kavi Arya / Krithi Ramamritham Use of Broadcasting Simplifies communication among concurrent modules Sender does not wait for the receiver Receiver does not care who the sender is Essentially like a shared variable but without associated problems Works because of synchrony hypothesis! Other problems creep in, of course!

© S. Ramesh / Kavi Arya / Krithi Ramamritham Causality Problems Non-reactive: signal S in present S then nothing else emit S end What is the behavior of this program? S is present iff it is not present

© S. Ramesh / Kavi Arya / Krithi Ramamritham Nondeterminism signal S in present S then emit S else nothing end S is emitted and is present or it is not emitted and it is not present both status are possible!

© S. Ramesh / Kavi Arya / Krithi Ramamritham Logical Correctness A program is logically correct if it is deterministic and reactive. Accepted programs should be logically correct The above programs are not logically correct and rejected by the compiler Some more additional restrictions They have to be acyclic

© S. Ramesh / Kavi Arya / Krithi Ramamritham Dependency Cycles [ present O1 then emit O2 end || present O2 else emit O1 end ] O2 is emitted if O1 is present O1 is emitted if O2 is not present cyclic dependency rejected by the compiler!

© S. Ramesh / Kavi Arya / Krithi Ramamritham More Acyclic programs Is the following program logically correct? input I; signal O1,O2 in present I then present O1 then emit O2 end else present O2 then emit O1 end end

© S. Ramesh / Kavi Arya / Krithi Ramamritham Cycles What about this? present O1 then emit O2; pause; present O2 then emit O1 They are accepted by the compiler! Compile-time cycles does not matter No run-time cycles allowed. Programs should be Constructively causal

© S. Ramesh / Kavi Arya / Krithi Ramamritham Constructive Causality [ present O1 then emit O1 end || present [O1 and not O2] then emit O2 end ] logically correct program but rejected It is not causal

© S. Ramesh / Kavi Arya / Krithi Ramamritham O1 O2 O1 = O1 O2 = O1 and not O2 O1 = 0 O1 = 1 ?

© S. Ramesh / Kavi Arya / Krithi Ramamritham Causality present S then emit S else emit S Is this equivalent to emit S? The former is rejected! The causality notion non trivial, More restrictive than logical correctness – Status of local signals should have unique values at every reaction step – Status determinable by a constructive deduction process