DIFFERENTIAL AMPLIFIERS

DIFFERENTIAL AMPLIFIER 1.VERY HIGH INPUT IMPEDENCE 2.VERY HIGH BANDWIDTH 3.DIFFERENTIAL INPUT 4.DC DIFFERENTIAL INPUT ACCEPTED 5.HIGH COMMON MODE REJECTION 6.SIGNAL INTEGRITY AT THE OUTPUT

Let us start with a simple amplifier that can give us at the output a signal proportional to the difference between two signals, each with reference to a ground. In a MOSFET under small signal conditions the output current is proportional to the signal voltage across the gate and source. As is obvious any signal applied to the source needs to be preferably applied through a buffer to reduce loading, while that at the gate could be applied directly.

It is evident from the circuit diagram that when we consider the output at transistor M 2, v o2, we are looking at a cascade of CD amplifier followed by CG amplifier from v s1 to v o2 and CS amplifier from v s2 to v 02. Similarly considering the output at transistor M 1, v o1, we are looking at a cascade of CD amplifier followed by CG amplifier from v s2 to v o1 and CS amplifier from v s1 to v 01. Assuming a total symmetrical circuit, it is sufficient to analyze the effect of any one signal input to analyze the total circuit. In analyzing the circuit we will use superposition theorem. Let us now look at the equivalent circuit and its analysis. We represent the current source I SS by its output impedance 1/g o in the equivalent circuit.

In the equivalent circuit Solving for v o1 /v s1 from the above three equations we get

Let us define the following: We can then write For a symmetric network A 11 = A 22 and A 12 = A 21.

We can now recast the equations as

The signal (v s1 – v s2 ) is called the differential signal and the signal (v s1 + v s2 ) is called the Common Mode signal. This leads us to define a very important parameter defining a differential Amplifier, the Common Mode Rejection Ratio, CMRR. CMRR is defined as Having evaluated the gains of differential and common mode gain an interesting fall out is what is popularly known as half circuit equivalent.

This has been reduced to two half circuits to evaluate differential and common mode gain. These are Differential Common Mode Half Circuit Half Circuit

The load Resistance used in a CMOS circuit could be each a PMOS transistor in saturation with a constant Gate to Source Voltage or Gate tied to Drain. In both these cases the load resistance is the same for M 1 and M 2.

Let us now consider an non- symmetric load on M 1 and M 2 and look at the outputs v o1 and v o2. For this circuit we will have

This will give us the outputs v o1 and v o2 as

Assuming that g m1 >> g o, the values of A d1, A d2, A CM1 and A CM2 reduce to Now since we are interested only in single ended output (say) v o2, we will device a useful method to use the other output to our advantage. What we would like to do is to connect the output v o1 to the gate of M 4. We will then get the most commonly used single ended differential amplifier structure overleaf.

Solving for the circuit assuming g m1, g m3 >> g o, g d1, g d3 we obtain the differential and common mode gain as

In our discussions so far we had considered NMOS input devices with PMOS load devices. It is equally likely that we may use PMOS input transistors and NMOS load transistors. The relative advantages of the NMOS input differential Amplifier and PMOS input Differential Amplifier will be seen as we go down the course.

NMOS input pair:

Common Mode Input Range

Lowest common mode input voltage at gate of M1(M2) v G1 (min) = V SS + v GS3 + v SD1 - v SG1 for saturation, the minimum value of v SD1 = v SG1 - |V T1 | Therefore, v G1 (min) = V SS + v GS3 - |V T1 | v G1 (max) = V DD - v SD5 - v SG1

Thermal Noise To reduce thermal noise we choose and large value of g m1.

Assume that V DD = 3V and that V SS = -3V. Using K’ N = 2K’ P 18 A/V 2, 0.8V <V TO3, V T1 < 1.2V, find the common mode range for worst case conditions. Assume that I SS = 100  A, W 1 /L 1 = W 2 /L 2 = 5, W 3 /L 3 = W 4 /L 4 = 1, and v SD5 = 0.2V.

The input common mode range is -0.25V to 0.6V.

Slew Rate: This defines the rate at which the load capacitor charged. In other words it defines the rate dv/dt at the output. Slew rate is a measure of the output to follow the input signal. This is normally associated with large signal property. Under large signal, only one of M 1 or M 2 will be ON and the charging current will be I 5. This gives a slew rate C L (V DD - V SS )/I 5.

Parasitic elements in the Differential Amplifier:

CT = tail capacitor (common mode only) CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3 COUT = output capacitor » Cbd4 + Cbd2 + Cgd2 + CL

Noise Sources in Differential Amplifiers:

Noise can be normally modeled as a current source in parallel to i D. This current source represents two sources of noise, thermal noise and flicker noise. The mean square current noise source is defined as The mean square noise reflected to the gate giving mean square voltage noise at the gate

The total output noise current, is obtained by summing each of the noise current contributions.

The total 1/f and thermal noise contributions can be written as

To get the input noise for NMOS input stages interchange B P for B N, K N ’ for K P ’ and vice versa. Since B N = 5B P it is preferable to use PMOS input stage to reduce 1/f noise with large area for M 1 and M 2 and 1/f Noise