Introduction to Avalon Interface Hardik Shah Robotics and Embedded Systems Department of Informatics Technische Universität München www6.in.tum.de 06 May.

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Presentation transcript:

Introduction to Avalon Interface Hardik Shah Robotics and Embedded Systems Department of Informatics Technische Universität München www6.in.tum.de 06 May 2013

What is On-chip Bus? 2 M1 M3 M2 Arbiter S1 S3 S2

What is On-chip Bus? 3 M1 M3 M2 Arbiter S1 S3 S2 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 Bottleneck

Slave-side Arbitration 4 M1 M3 M2 Arbiter S1 S3 S2 Arbiter

Avalon Signals  ONLY a master initiates a transaction 5 Master Avm_Address (Byte) Avm_Byte_Enable Avm_Write Avm_Read Avm_Write_Data Avm_Read_Data Avm_Wait Avm_Read_Data_Valid Master Avm_Address (Byte) Avm_Byte_Enable Avm_Write Avm_Read Avm_Write_Data Avm_Read_Data Avm_Wait Avm_Read_Data_Valid Slave Avs_Address (Word) Avs_Chip_Select Avs_Byte_Enable Avs_Write Avs_Read Avs_Write_Data Avs_Read_Data Avs_Wait Avs_Read_Data_Valid Slave Avs_Address (Word) Avs_Chip_Select Avs_Byte_Enable Avs_Write Avs_Read Avs_Write_Data Avs_Read_Data Avs_Wait Avs_Read_Data_Valid Clock, Reset

Basic transfers 6

Pipelined Transfers 7

How to Integrate with SOPC/QSyS 8

9

10

How to Integrate with SOPC/QSyS 11

How to Integrate with SOPC/QSyS 12

Thank you. Questions ? 13