JAZiO ™ Incorporated 1 JAZiO I/O Switching Technology

JAZiO ™ Incorporated 2 What Makes I/O? API HAL Topology Protocol Link Layer Physical Layer Logical Spec Transport Spec Electrical Spec Switching Technology Switching Technology Determines I/O Performance Why Is Switching Technology Important? I/O performance may determine: Product Performance

JAZiO ™ Incorporated 3 Switching Technologies Dominant switching technologies today: –Differential –Pseudo-Differential JAZiO technology is now available to challenge these current leaders

JAZiO ™ Incorporated 4 Differential  Fully differential receiver  Great for simultaneous switching  But two pins per data bit Data0 - + DataN - + CLK - + Latching TransmitterReceiver Used in: HyperTransport RapidIO SPI-4 Phase 2 LVDS Serial Channels Etc.

JAZiO ™ Incorporated 5 Pseudo-Differential  Constant VREF  Less-precise receiver  One pin per data bit CLK - + Latching TransmitterReceiver Data0 DataN VREF Used in: GTL PCI AGP SPI-4 Phase 1 Rambus RSL DDR Etc.

JAZiO ™ Incorporated 6 JAZiO Technology  Voltage/Timing References  Two differential receivers per bit  One pin per data bit Can be used: Anywhere that Pseudo-Differential Or Differential Are used VTR VTR- VTR TransmitterReceiver Data0 DataN Data0 DataN Except Serial Channels

JAZiO ™ Incorporated 7 Three I/O Switching Technologies VTR R D0 VTR- R D15 JAZiO 18 Pins VREF R D0 R D15 Pseudo- Differential 19 Pins CLK- CLK R D0- D0 R D15- D15 CLK- CLK 34 Pins Differential 16 Bits of Each

JAZiO ™ Incorporated 8 JAZiO Solution Data is driven coincidentally with these VTRs Data Input Like Differential except:  VTR stands in for all the complements going in one direction  VTR- stands in for all the complements going in the other direction VTR - Provide alternating Voltage/Timing References switching at the data rate One Bit Time Next Bit Time VTR Two White Papers at Two Differential Comparators are used The Blue Box selects the right comparator Data Output VTR VTR - VTR A SL - XorB in out Data Input VTR XorA B SL Steering Logic Per Bit Per 4 Bits

JAZiO ™ Incorporated 9 The receiver cell is: 22um x 55um (Including routing channels) A pad cell is: 70um x 80um A JAZiO receiver is 22% of the area of a bonding pad

JAZiO ™ Incorporated 10 JAZiO vs Differential So is JAZiO like Differential except with one pin per data bit? No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present

JAZiO ™ Incorporated 11 Attenuation/ISI Source Destination Lone Pulse Source Destination Midpoint Continuous Pulses Signal at Destination is Centered Around the Midpoint

JAZiO ™ Incorporated 12 MIDPOINT DATA DATA- Differential MIDPOINT DATA VTR JAZiO VREF Pseudo- Differential DATA Data Eye with Attenuation/ISI Continuous Pulse EYE JAZiO Has MUCH Larger Worst-Case Data Eye ~40% Attenuation Lone Pulse EYE Signals driven the same for all three technologies

JAZiO ™ Incorporated 13 JAZiO vs Differential So is JAZiO like Differential except with one pin per data bit? No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present A larger data eye can be used to: 1.Increase data rate 2.Reduce power 3.Increase robustness 4.Reduce complexity Or all four!!!

JAZiO ™ Incorporated 14 Parallel vs Serial Interface JAZiO is for parallel interfaces Some claim that high speed interconnect must be serial due to large bit-to-bit skew This leads to encoded serial data on a differential pair and, sometimes, bundles of serial channels Also leads to complexity, power, and large latency JAZiO can deal with skew and retain the benefits of low latency, parallel interface

JAZiO ™ Incorporated 15 JAZiO Deals with Skew JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint

JAZiO ™ Incorporated 16 Late Data Midpoint Level Bit-to-Bit Skew Signals Driven Identically For:  JAZiO  Differential  Pseudo-Diff CONCLUSION: JAZiO is Inherently More Immune to Skew VREF Eye Opening Variance Differential or Pseudo-Diff VTR Early Data No-Skew Data Eye Opening Variance JAZiO NOTE: Same Variances At Trailing Edge

JAZiO ™ Incorporated 17 JAZiO Deals with Skew JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination

JAZiO ™ Incorporated 18 JAZiO Receiver Monitor Data Output VTR - A XorB in out Data Input VTR XorA B Receiver Monitor XORs Provide Receiver Monitor (Feedback to Source) Can Detect Marginalities In System During Operation Before Failure See White Papers at

JAZiO ™ Incorporated 19 JAZiO Deals with Skew JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination JAZiO can use two-VTR pairs offset in time and tuning cycles can be used to select the best pair on each bit

JAZiO ™ Incorporated 20 Destination Deskew with Two VTR Pairs Data In VTR2 R R VTR1 Select Data Out R2 VTR Pairs offset in time selected using receiver monitor See White Papers at

JAZiO ™ Incorporated 21 Parallel vs Serial A serial channel at 10 Gbps likely uses a differential pair and transmits 10 bits for every 8 bits of data (encoding) Actual data rate per pin is 4 Gbps with huge die size, latency, and complexity penalties JAZiO second generation provides same data rate per pin without die size or latency penalty – and is easily expanded as wide as desired Conclusion: No need for serial to invade the traditional domain of parallel buses

JAZiO ™ Incorporated What’s Needed for Finished Product? Pseudo-Diff Technology Small Eye 1 Pin/Bit Differential Technology Medium Eye 2 Pins/Bit JAZiO Technology Switching Technology Enhancements Pre-E, Deskew, … Engineering Finished Product Enhancements Pre-E, Deskew, … Lots of Engineering Mediocre Product Enhancements Pre-E, Deskew, … Lots of Engineering Expensive Product Enhancements Pre-E, Deskew, … Less Engineering Great Product Large Eye 1 Pin/Bit Data Eye Pins/Bit

JAZiO ™ Incorporated 23 First Ever JAZiO Silicon Results Demo Chip:0.18u TSMC, Standard ESD Enhancements:No pre-emphasis, encoding, or deskew Package:120 Pin TQFP, 5nH Center-8nH Corner, <$1.00 PC Board: FR4, No isolation between signals Previous highest known data rate with these conditions: <400 Megabits/sec/pin Lowest cost, Highest availability components PAT GEN DRVRs RING OSC M/S MASTER PAT GEN RCVRs COMP M/S SLAVE DATA (16) VTR (2) 9” BER

JAZiO ™ Incorporated 24 Power = 20 mW/bit Skew = 285 pS Data Rate = 1.5 Gigabits/Sec/Pin Results VTR VTR -

JAZiO ™ Incorporated 25 JAZiO Roadmap 1 st Generation Basic JAZiO 0.18u + BGA 2 Gb/sec/pin rd Generation Deskew Pre-emphasis Dual VTR 0.10u + FC BGA 6 Gb/sec/pin nd Generation Deskew Simple Pre-emphasis 0.13u + BGA 4 Gb/sec/pin 2003 Data Rate Per Pin Time

JAZiO ™ Incorporated 26 Announcements Dolphin Technology ( –JAZiO design services partner –Developing Super PHY with JAZiO technology Alliance Semiconductor ( –1 st JAZiO licensee –Developing high BW SRAM with JAZiO interface –Sampling in Q2, 2002

JAZiO ™ Incorporated 27 Summary JAZiO is basic I/O technology from which excellent parallel buses can be built Using JAZiO, parallel buses can achieve very high performance – no need to move to serial buses JAZiO technology, with large data eye and pin efficiency, is the highest performance and lowest cost technology available