Part One. HOMEWORK 1 PART B 1. Compute the following using pipeline method a. e. i.12/4 b. f. J.49/7 c. g.3*10 d. h.91*14 2. Illustrate the generation.

Slides:



Advertisements
Similar presentations
Three Special Functions
Advertisements

Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika
Prof. Sin-Min Lee Department of Computer Science
Combinational Logic Circuits Chapter 2 Mano and Kime.
التصميم المنطقي Second Course
Proving Incompleteness {NAND} is a complete system Is {XOR,0} a complete system?
Computer Engineering (Logic Circuits) (Karnaugh Map)
Part 2: DESIGN CIRCUIT. LOGIC CIRCUIT DESIGN x y z F F = x + y’z x y z F Truth Table Boolean Function.
CS 105 Digital Logic Design
BOOLEAN FUNCTION PROPERTIES
Logic Design CS221 1 st Term K-Map Cairo University Faculty of Computers and Information.
Chapter 2 Combinational Systems And / Or / Not. TRIAD PRINCIPLE: Combinational is about And / Or / Not combinations As well as equivalent functions. It.
Combinational Logic Design
1 COMBINATIONAL LOGIC One or more digital signal inputs One or more digital signal outputs Outputs are only functions of current input values (ideal) plus.
Sahar Mosleh PageCalifornia State University San Marcos 1 Multiplexer, Decoder and Circuit Designing.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC. K-Map (1)  Karnaugh Mapping is used to minimize the number of logic gates that are required in a digital circuit.
Discrete Mathematics CS 2610 February 19, Logic Gates: the basic elements of circuits Electronic circuits consist of so-called gates connected.
F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ + X = 1.
Chapter 10 (Part 2): Boolean Algebra  Logic Gates (10.3) (cont.)  Minimization of Circuits (10.4)
EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 4: Other Gates.
Chapter 3 Gate-Level Minimization
Computer Engineering (Logic Circuits) (Karnaugh Map)
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
1 EG 32 Digital Electronics Thought for the day You learn from your mistakes..... So make as many as you can and you will eventually know everything.
Sneha.  A combinational circuit that performs the addition of two bits is called a half adder.  It has two inputs.  It has two outputs.
Computer Systems 1 Fundamentals of Computing Simplifying Boolean Expressions.
Boolean Algebra & Logic Circuits Dr. Ahmed El-Bialy Dr. Sahar Fawzy.
1 Chapter 4 Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables,
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC
Key Observation Adjacencies in the K-Map
Karnaugh Map (K-Map) By Dr. M. Khamis Mrs. Dua’a Al Sinari.
Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.
ECE DIGITAL LOGIC LECTURE 8: BOOLEAN FUNCTIONS Assistant Prof. Fareena Saqib Florida Institute of Technology Spring 2016, 02/11/2016.
1 CS 352 Introduction to Logic Design Lecture 2 Ahmed Ezzat Boolean Algebra and Its Applications Ch-3 + Ch-4.
©2010 Cengage Learning SLIDES FOR CHAPTER 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use.
UNIT 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.
©2010 Cengage Learning SLIDES FOR CHAPTER 3 BOOLEAN ALGEBRA (continued) Click the mouse to move to the next page. Use the ESC key to exit this chapter.
Mu.com.lec 9. Overview Gates, latches, memories and other logic components are used to design computer systems and their subsystems Good understanding.
Presented by A. Maleki Fall Semester, 2010
Mantıksal Tasarım – BBM231 M. Önder Efe
Objectives The student will be able to:
8.2A Factoring using Distributive Property
Assembly Lab1 - Review.
Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章(Chapter 58) 伏者潛藏也
FIGURE 3.1 Two-variable K-map
Table 2.1 Postulates and Theorems of Boolean Algebra
ECE 3130 Digital Electronics and Design
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
Computer Organisation
Prof. Sin-Min Lee Department of Computer Science
CS 352 Introduction to Logic Design
Part 4 Combinational Logic.
Combinational Logic Circuits
Computer Architecture CST 250
Drawing Triangles.
Lecture 14: Boolean Algebra
Adders and Subtractors
Table 2.1 Postulates and Theorems of Boolean Algebra
Objectives The student will be able to:
Objectives The student will be able to:
Bell Ringer 10/27/10 What is the GCF? 18x³y² and 24x² ab and a³b².
Warm Up Rewrite -6x + 2x3 + 1 – 9x in standard form, then name by degree & number of terms. 2) Multiply (x + 3)(5x – 1) 3) Multiply (x – 1)(4x2 +5x –
Factoring Polynomials.
Chapter-4 Combinational Logic
Objectives The student will be able to:
Factoring using the greatest common factor (GCF).
Objectives The student will be able to:
Objectives The student will be able to:
Objectives The student will be able to:
Presentation transcript:

Part One

HOMEWORK 1 PART B 1. Compute the following using pipeline method a. e. i.12/4 b. f. J.49/7 c. g.3*10 d. h.91*14 2. Illustrate the generation of 4 variable Dertouzos Table 3. Realize XOR using threshold gates 4. Realize half subtractor as a cascade of threshold gates. 5. Realize full subtractor as a cascade of threshold gates.

6. Realize the following functions in cascade : f1 = X1’X2’X4 f2 = X2X3’X4’ f3 = X1X2X3 7. realize as a cascade of threshold gates: S = A C0 = A’( 8. realize as a cascade of three threshold gates: f = (0,3,4,7,9,13)

ANSWER TO QUESTION ONE Rooting a F1=1 Answer : F2 = F3 = F4 = 1

b F1= F2 = F3 = 0 Answer : F4 = 0

c F1=1 Answer : F2 = F3 = F4 = F5 = 0

d F1=1 Answer : F2 = F3 = 1

Squaring e. 1 F1 F2 Answer : 0 1 (F1 = 1) (F2 = 1)

f F1 F2 F3 F4 Answer : 01 F1= F2= F3= F4=

Multiplication g. 3*10 Answer : Left shift Right shift

H 91*

DIVISION I.12/ > > F1= F2=1 Answer: 1100/100 = > 3 10

J.49/ F1=0 Answer : /111 = > F2= F3= F4=1

ANSWER TO QUESTION NUMBER TWO Arbitrary weight for W0 <= W1 <= W2 are chosen W0=40, W1=50, W2=60 Atable of weighted sum is built for the possible minterm in 3 variables. Upper threshold limit is selected 150/2 = 75. A list of test threshold that fall between the weighted sums that are less than 75 is constructed : (-1, 20, 45, 55, 75) For each test threshold, a truth table is created, such that a true value is obtained if that minterms weight sum is less than test threshold.

To calculate b’s T=-1 b0=(2x0)-8=-8 b= 8, 0, 0, 0 ---(1) T=20 b0=(2x1)-8=-6 b=6, 2, 2, 2 ---(2) b1,2,3=2(0-1)=-2 T=45 b0=2x2-8=-4 b=4, 4, 4, 0 ---(3) b1=2(0-2)=4 b2=2(0-2)=4 b3=2(1-1)=0 T=55 b0=2x3-8=-2 b=2, 6, 2, 2 ---(4) b1=2(0-3)=-6

b2=2(1-2)=-2 b3=2(1-2)=-2 T=75 b0=2x4-8=0 b=0, 4, 4, 4 ---(5) b1=2(1-3)=-4 b2=2(1-3)=-4 b3=2(1-3)=-4

Each vector is then sorted in decending order and duplicates are eliminated

ANSWER TO QUESTION NUMBER THREE Realization of XOR f=x’y+xy’ Take each minterm and realize it with one threshold gate, and then OR them f1=x’y, f2=xy’ f1: 0 1 x /2 N(1) 0 1 N(0) 1 0 y 1 1 1/2 T=0.5 x 1 1 1/2 f2: y -1 N(1) 1 0 N(0) 0 1 T=0.5

ANSWER TO QUESTION NO 4 Realiazation of half subtractor B=x’y D=x’y-xy’=B+xy’ For B=x’y Determine positive function B=xy Find all Minimum True and Maximum False vertices x y The Inequalities: 0 0 Wx + Wy > Wy => Wx > 0 F 0 1 W x + Wy > Wx => Wy > 0 F 1 0 Choose Wx = Wy = 1 Tmin 1 1

So, UL = 1x1 + 1x1 = 2 For every input which is complimented in the original function, its weight LL = 1x1 + 0x1 = 1 must be changed to -W and T to T-W T = 3/2 Wx = -1, Wy = 1, T = 1/2

For D = B + xy’ Generate the truth table for the 3-variable B, x, y and find the Minimum True and Maxumum False vertices The positive function: D = B + xy Tmin Fmax

The inequalities : W3 > W1 W3 > W2 W1 + W2 > W1 => W2 > 0 W1 + W2 > W2 => W1 > 0 choose W1 = W2 = 1, W3 = 2 UL = 1, LL = 2, T = 3/2 Architecture of Half-Subtractor :

REALIZE OF A FULL ADDER S1=A’B’C’+C0 S1= =(A+B+C) C0’ S= (A+B+C) C0’

REALIZATION OF FULL SUBTRACTOR B = x’y + x’z + yz D = x’y’z + x’yz’ + xyz + xy’z’ Let, D1 = D + x’yz = x’y’z + x’yz’ + xyz + xy’z’ + x’yz D1 = B + xy’z’ D = (B + xy’z’) - x’yz D = (B + xy’z’)(x + y’ + z’)

Unate N(1) N(0)

b0 = 2x = 0 b4 b3 b2 b1 b0 b1 = 2(5-3) = b2 = b3 = -4 a4 a3 a2 a1 a0 b4 = 12

REALIZATION OF THE FOLLOWING THREE FUNCTION IN CASCADE f1 = x1’ x2’ x4 f2 = x2 x3’ x4’ f3 = x1 x2 x3 1.f1 = x1’ x2’ x4 Positive function f1 = x1 x2 x4 Tmin Fmax The inequalities: W1 + W2 + W4 > W1 + W2 + W3 => W4 > W2 W1 + W2 + W4 > W1 + W3 + W4 => W2 > W3 W1 + W2 + W4 > W2 + W3 + W4 => W1 > W3 W3 = 0 W1 = W2 = W4 = 1 UL = 3, LL = 2, T = 5/2

f2=x2x1’x4’ f3=x1x2x3

Now we can cascade the three threshold gates in any order f1->f2->f3 or f3->f1->f2-> or f2->f3->f1

REALIZE AS A CASCADE OF THRESHOLD GATES let

REALIZE AS A CASCADE OF THREE THRESHOLD GATES 1. Positive function f1=xwz Tmin = Fmax =

The iequalities W1+W3+W4 > W1+W2 +W3 => W4 > W2 W1+W3+W4 > W1+W2 +W4 => W4 > W2 W1+W3+W4 > W1+W2 +W3 => W4 > W2 Choose W2 = 0 W1=W3=W4=1 UL=3, LL=2, T=5/2

Now, let the cascade gates be in f1 -> f2 -> f3 ->

To determine the weight for f1: (-1) (0) (1) (1) x y z w The minterms f1 + 0 > 1.5 & both f1 & f f1 + 2 > f1 + 2 > f1 + 2 > 1.5 min weight for f1=2 for minimum weight for f2: (1) (0) (-1) (1) x y z w f2 + 0 > f2 + 0 > f2 + 2 > f2 + 2 > 1.5 min weight for f2=2

Part Two

HALF ADDER Create truth table for half adder Expand truth table to three inputs. Terms not found on first table are assigned as don’t care terms for S. S=XC’ + YC’ S=(X + Y)C’

FULL ADDER Create truth table for full adder C=XY + YZ + XZ

FULL ADDER Expand truth table to four inputs. Terms not found on first table are assigned as don’t care terms for S. S = XC’ + YC’ + ZC’ + XYZ S = (X + Y + Z)C’ + XYZ

HALF SUBTRACTOR Create truth table for half subtractor. Expand truth table to three inputs. Terms not found D = X’Y on first table are assigned as don’t care terms for D. D = XY’ + B

FULL SUBTRACTOR Create truth table for full subtractor B = X’Y + X’Z + YZ

FULL SUBTRACTOR Expand truth table to four inputs. Terms not found on first table are assigned as don’t care terms for D. D = Z’B + XB + Y’B +XY’Z’ D = (X + Y’ + Z’)B + XY’Z’

PART THREE

Q. Write down the detailed steps for BDD of the majority function Solution: f= Assume: X1=A’B, X2=C, X3=D’E+DF M(A’B, C, D’E+DF)=X1X2+X1X3+X2X3

The total result f=

Arithmatic cell: BDD for Fi=CoX+PiX’ D=C(B+Fi) Control cell: Fi=CoX+PiX’ E=B(C+C’)+Cfi=BC’+D

Implementation: “One-out-of-two” Selector f=(Vv g)(V’ v h) E : Check: E=(B+D)(B’+(C+1)(C’+)) =(B+D)(B’+C’+D) =BC’+D =BC’+C(B+Fi) =B+Cfi D:

Fi: Co:

S:

Interconnection: