5-1 Memory System

Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable) 1M x 8 Address Bus (A0 – A19) Data Bus ( D0 – D7)

Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable) 512K x 8 Address Bus (A0 – A19) D0 – D7 512K x 8 Data Bus (D0 – D15) D8 – D15

Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable) 512K x 8 Address Bus (A0 – A19) D0 – D7 512K x 8 Data Bus (D0 – D15) D8 – D15 Bank 0Bank 1 EVEN addresses goes to bank 0 ODD addresses goes to bank 1

AL Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable) 512K x 8 Address Bus (A0 – A19) D0 – D7 512K x 8 Data Bus (D0 – D15) D8 – D15 AH Bank 0Bank 1 EVEN addresses goes to bank 0 ODD addresses goes to bank 1 MOV [1000], AX DS:1000 = AL DS:1001 = AH

AH Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable) 512K x 8 Address Bus (A0 – A19) D0 – D7 512K x 8 Data Bus (D0 – D15) D8 – D15 AL Bank 0Bank 1 EVEN addresses goes to bank 0 ODD addresses goes to bank 1 MOV [1001], AX DS:1001 = AL DS:1002 = AH

BHE'A0Function 00 Both banks are enabled for a 16-bit transfer 01 High bank enabled for an 8-bit transfer 10 low bank enabled for an 8-bit transfer 11No banks enabled

5-9 Designing Larger Memories 64M X 32 memory using 16M X 16 chips

5-10 Memory Mapping Full mapping

5-11 Memory Mapping (cont’d) Partial mapping

5-12 Interleaved Memory In our memory designs – Block of contiguous memory addresses is mapped to a module One advantage – Incremental expansion Disadvantage – Successive accesses take more time » Not possible to hide memory latency Interleaved memories – Improve access performance Allow overlapped memory access Use multiple banks and access all banks simultaneously – Addresses are spread over banks » Not mapped to a single memory module

5-13 Interleaved Memory (cont’d)

5-14 Interleaved Memory (cont’d) Interleaved memory allows pipelined access to memory

5-15 Interleaved Memory (cont’d) Number of banks – M = memory access time in cycles – To provide one word per cycle Number of banks  M Drawbacks of interleaved memory – Involves complex design Example: Need MDR or MAR – Reduced fault-tolerance One bank failure leads to failure of the whole memory – Cannot be expanded incrementally

Static RAM (SRAM) Essentially uses flip-flops to store charge (transistor circuit) As long as power is present, transistors do not lose charge (no refresh) Very fast (no sense circuitry to drive nor charge depletion) Complex construction Large bit circuit Expensive Used for Cache RAM because of speed and no need for large volume

5-17 Static RAM Structure six transistors per bit (flip flop) “NOT” /1 = example

Dynamic RAM (DRAM) Bits stored as charge in capacitors Simpler construction Smaller per bit Less expensive Slower than SRAM Typical application is main memory Essentially analogue -- level of charge determines value

5-19 Dynamic RAM Structure one transistor and one capacitor per bit ‘High’ Voltage at Y allows current to flow from X to Z or Z to X X Y Z +

5-20 SRAM v.s. DRAM Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Storage element Advantages 1.Fast 2.No refreshing operations 1.High density and less expensive Disadvantages 1.Large silicon area 2.expensive 1.Slow 2.Require refreshing operations Applications High speed memory applications, Such as cache Main memories in computer systems

5-21 DRAM Organisation Two dimensional matrix Bits are accesses by: cas –Accepting row and column addresses down the same multiplexed address bus –First: Row address is presented and latched by ras signal –Next: column address is presented and latched by cas signal

5-22 Typical 16 Mb DRAM (4M x 4) 2 k x 2 k = 4 M RAS = Row Addr. Select CAS = Column Addr. Select WE = Write Enable OE = Output Enable nybble

5-23 Accessing DRAMs  DRAM block diagram Addr[7:0] CAS RAS Storage Array Column decoder Row decoder

5-24 Accessing DRAMs  Address bus selection circuit QDQD CLK set QD Q decoder address IO/M RAS CAS To DRAM Row Address Column Address MUX

5-25 Accessing DRAMs  Refreshing operations — Because leakage current will destroy information stored on DRAM capacitors periodic refreshing operations are required for DRAM circuits — During refreshing operation, DRAM circuit are not able to response processor’s request to perform read or write operations — How to suspend memory operations? — DRAM controllers are developed to take care DRAM refreshing operations

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