VHDL Structural Architecture ENG241 Week #5 1. Fall 2012ENG241/Digital Design2 VHDL Design Styles Components and interconnects structural VHDL Design.

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Presentation transcript:

VHDL Structural Architecture ENG241 Week #5 1

Fall 2012ENG241/Digital Design2 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral (algorithmic) Registers State machines Test benches Sequential statements Subset most suitable for synthesis

Fall entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity decoder_2_to_4; architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity decoder_2_to_4; architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; Decoder: Data Flow Example: 2-to-4 decoder D0 D1 D2 D3 A(1) A(0) Interface Functionality A0_n A1_n

Fall 2012ENG241/Digital Design4 Structural VHDL Description of 2-to-4 Line Decoder

Fall 2012ENG241/Digital Design5 Structural VHDL Description (Entity Declaration) -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;

Fall 2012ENG241/Digital Design6 Structural VHDL Description (Signals) A0_n A1_n N0 N3 N1 N2

Fall 2012ENG241/Digital Design7 Structural VHDL Description (Components) architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component;

Fall 2012ENG241/Digital Design8 Structural VHDL Description (Connecting components) architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;

Fall 2012ENG241/Digital Design9 Example – 4-bit Equality Specifications:  Input: 2 vectors A(3:0) and B(3:0)  Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise

Fall 2012ENG241/Digital Design10 Design Hierarchical design seems a good approach Decompose the problem into four 1-bit comparison circuits and an additional circuit that combines the four comparison circuit outputs to obtain E. 1.One module/bit 2.Final module for E

Fall Design for MX module Logic function is  Can implement as Define the output of the circuit to be `0’ if both inputs are similar and `1’ if they are different?

Fall 2012ENG241/Digital Design12 Design for ME module Final E is 1 only if all intermediate values are 0 So And a design is

Fall 2012ENG241/Digital Design13 Overall Design

Fall entity mx_module is port ( Ai, Bi: in std_logic; Ei : out std_logic); end entity mx_module; architecture dataflow of mx_module is Signal Ai_n, Bi_n, ND_1, ND_2: std_logic; begin Ai_n <= not Ai; Bi_n <= not Bi; ND_1 <= Ai and B_n; ND_2 <= Bi and A_n; Ei <= ND_1 or ND_2; end architecture dataflow; entity mx_module is port ( Ai, Bi: in std_logic; Ei : out std_logic); end entity mx_module; architecture dataflow of mx_module is Signal Ai_n, Bi_n, ND_1, ND_2: std_logic; begin Ai_n <= not Ai; Bi_n <= not Bi; ND_1 <= Ai and B_n; ND_2 <= Bi and A_n; Ei <= ND_1 or ND_2; end architecture dataflow; MX Module: Data Flow Interface Functionality Bi_n Ai_n ND_1 ND_2

15 entity ME_module is port ( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); E: out std_logic); end entity mx_module; architecture structural of ME_module is component mx_module port ( Ai, Bi: in std_logic; Ei : out std_logic); end component; Signal E0,E1,E2,E3: std_logic; begin mx0: mx_module port map (A(0), B(0), E0); mx1: mx_module port map (A(1), B(1), E1); mx2: mx_module port map (A(2), B(2), E2); mx3: mx_module port map (A(3), B(3), E3); E <= E0 nor E1 nor E2 nor E3; end architecture structural; entity ME_module is port ( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); E: out std_logic); end entity mx_module; architecture structural of ME_module is component mx_module port ( Ai, Bi: in std_logic; Ei : out std_logic); end component; Signal E0,E1,E2,E3: std_logic; begin mx0: mx_module port map (A(0), B(0), E0); mx1: mx_module port map (A(1), B(1), E1); mx2: mx_module port map (A(2), B(2), E2); mx3: mx_module port map (A(3), B(3), E3); E <= E0 nor E1 nor E2 nor E3; end architecture structural; ME Module: Structural Interface Functionality