Cache Optimization Summary Technique MR MP HT Complexity Larger Block Size + – 0 Higher Associativity + – 1 Victim Caches + 2 Pseudo-Associative Caches + 2 HW Prefetching of Instr/Data + 2 Compiler Controlled Prefetching + 3 Compiler Reduce Misses + 0 Priority to Read Misses + 1 Subblock Placement + + 1 Early Restart & Critical Word 1st + 2 Non-Blocking Caches + 3 Second Level Caches + 2 Small & Simple Caches – + 0 Avoiding Address Translation + 2 Pipelining Writes + 1 miss rate penalty miss hit time

Small-Scale—Shared Memory Caches serve to: Reduce latency of access Valuable for both private (by single processor) data and shared (by multiple processors) data What about cache consistency?

S/W solutions Compiler tags data as cacheable and non-cacheable Only read-only data is considered cacheable and put in private cache All other data are non-cacheable, and can be put in a global cache

Potential HW Coherency Solutions Snooping Solution (Snoopy Bus): Send all requests for data to all processors Processors snoop to see if they have a copy and respond accordingly Requires broadcast, since caching information is at processors Works well with bus (natural broadcast medium) Dominates for small scale machines (most of the market) Directory-Based Schemes Keep track of what is being shared in 1 centralized place (logically) Distributed memory => distributed directory for scalability (avoids bottlenecks) Send point-to-point requests to processors via network Scales better than Snooping Actually existed BEFORE Snooping-based schemes

Bus Snooping Topology Memory: centralized with uniform access time (“UMA”) and bus interconnect Examples: Sun Enterprise 5000, SGI Challenge, Intel SystemPro

Basic Snoopy Protocols Write Invalidate Protocol: Multiple readers, single writer Write to shared data: an invalidate is sent to all caches which snoop and invalidate any copies Read Miss: Write-through: memory is always up-to-date Write-back: snoop in caches to find most recent copy Write Broadcast Protocol (typically write through): Write to shared data: broadcast on bus, processors snoop, and update any copies Read miss: memory is always up-to-date Write serialization: bus serializes requests! Bus is single point of arbitration

Basic Snoopy Protocols Write Invalidate versus Broadcast: Invalidate requires one transaction per write-run Invalidate uses spatial locality: one transaction per block Broadcast has lower latency between write and read

Write-Invalidation Protocol with write-back

Write-Broadcast Protocol with write-back

An Example Snoopy Protocol Invalidation protocol, write-back cache Each block of memory is in one state: Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches Each cache block is in one state (track these): Shared : block can be read OR Exclusive : cache has only copy, its writeable, and dirty OR Invalid : block contains no data Read misses: cause all caches to snoop bus Writes to clean line are treated as misses

Snoopy-Cache State Machine-I CPU Read hit State machine for CPU requests for each cache block CPU Read Shared (read/only) Invalid Place read miss on bus CPU Write CPU read miss Write back block, Place read miss on bus Place Write Miss on bus CPU Read miss Place read miss on bus Invalid: read => shared write => dirty shared looks the same CPU Write Place Write Miss on Bus Cache Block State Exclusive (read/write) CPU Write Miss Write back cache block Place write miss on bus CPU read hit CPU write hit

Snoopy-Cache State Machine-II State machine for bus requests for each cache block Write miss for this block Shared (read/only) Invalid Write miss for this block Write Back Block; (abort memory access) Read miss for this block Write Back Block; (abort memory access) Exclusive (read/write)

Snoopy-Cache State Machine-III CPU Read hit State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared (read/only) Invalid CPU Read Place read miss on bus CPU Write Place Write Miss on bus Write miss for this block CPU read miss Write back block, Place read miss on bus CPU Read miss Place read miss on bus Write Back Block; (abort memory access) CPU Write Place Write Miss on Bus Invalid: read => shared write => dirty shared looks the same Cache Block State Write Back Block; (abort memory access) Read miss for this block Exclusive (read/write) CPU Write Miss Write back cache block Place write miss on bus CPU read hit CPU write hit

Example Processor 1 Processor 2 Bus Memory Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back CPU Write Miss CPU Read Miss Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2

Example: Step 1 Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back CPU Write Miss CPU Read Miss Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2. Active arrow =

Example: Step 2 Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back CPU Write Miss CPU Read Miss Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2

Example: Step 3 Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2. CPU Read Miss CPU Write Miss Write Back

Example: Step 4 Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2 CPU Read Miss CPU Write Miss Write Back

Example: Step 5 Assumes initial cache state Remote Write Write Back Remote Write Invalid Shared Exclusive CPU Read hit Read miss on bus Write miss on bus CPU Write Place Write Miss on Bus CPU read hit CPU write hit Remote Read Write Back Assumes initial cache state is invalid and A1 and A2 map to same cache block, but A1 != A2 CPU Read Miss Why write miss first? Because in general, only write a piece of block, may need to read it first so that can have a full vblock; therefore, need to get Write back is low priority event. CPU Write Miss Write Back

Snooping Cache Variations Basic Protocol Exclusive Shared Invalid Berkeley Protocol Owned Exclusive Owned Shared Shared Invalid Illinois Protocol Private Dirty Private Clean Shared Invalid MESI Protocol Modfied (private,!=Memory) Exclusive (private,=Memory) Shared (shared,=Memory) Invalid Owner can update via bus invalidate operation Owner must write back when replaced in cache If read sourced from memory, then Private Clean if read sourced from other cache, then Shared Can write in cache if held private clean or dirty

Snoop Cache Extensions CPU Read hit Extensions: Fourth State: Ownership Remote Write or Miss due to address conflict Shared (read/only) Shared-> Modified, need invalidate only (upgrade request), don’t read memory Berkeley Protocol Invalid CPU Read Place read miss on bus CPU Write Place Write Miss on bus Cache supplies data when shared state (no memory access) Illinois Protocol Remote Write or Miss due to address conflict Write back block Remote Read Place Data on Bus? Remote Read Write back block Clean exclusive state (no miss for private data on write) MESI Protocol CPU Write Place Write Miss on Bus Modified (read/write) Exclusive (read/only) CPU read hit CPU write hit CPU Write Place Write Miss on Bus? CPU Read hit

Implementing Snooping Caches Multiple processors must be on bus, access to both addresses and data Add a few new commands to perform coherency, in addition to read and write Processors continuously snoop on address bus If address matches tag, either invalidate or update Since every bus transaction checks cache tags, could interfere with CPU cache access: solution 1: duplicate set of tags for L1 caches just to allow checks in parallel with CPU solution 2: L2 cache already duplicate, provided L2 obeys inclusion with L1 cache block size, associativity of L2 affects L1

Implementing Snooping Caches Bus serializes writes, getting bus ensures no one else can perform memory operation On a miss in a write back cache, may have the desired copy and its dirty, so must reply Add extra state bit to cache to determine shared or not Add 4th state (MESI)

Implementing Snoopy Caches Main structure for a snoop-based cache coherence algorithm.

Larger MPs Separate Memory per Processor Local or Remote access via memory controller Alternative: directory per cache that tracks state of every block in every cache Which caches have a copies of block, dirty vs. clean, ... Info per memory block vs. per cache block? PLUS: In memory => simpler protocol (centralized/one location) MINUS: In memory => directory is ƒ(memory size) vs. ƒ(cache size) Prevent directory as bottleneck? distribute directory entries with memory, each keeping track of which Procs have copies of their blocks

Distributed Directory MPs

Directory Protocol Similar to Snoopy Protocol: Three states Shared: ≥ 1 processors have data, memory up-to-date Uncached (no processor has it; not valid in any cache) Exclusive: 1 processor (owner) has data; memory out-of-date In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy) Keep it simple(r): Writes to non-exclusive data => write miss Processor blocks until access completes Assume messages received and acted upon in order sent

Directory Protocol No bus and don’t want to broadcast: interconnect no longer single arbitration point all messages have explicit responses Terms: typically 3 processors involved Local node where a request originates Home node where the memory location of an address resides Remote node has a copy of a cache block, whether exclusive or shared Example messages on next slide: P = processor number, A = address

Basic Scheme (Censier & Feautrier) • Assume "k" processors. • With each cache-block in memory: k presence-bits, and 1 dirty-bit • With each cache-block in cache: 1valid bit, and 1 dirty (owner) bit Read from main memory by PE-i: If dirty-bit is OFF then { read from main memory; turn p[i] ON; } if dirty-bit is ON then { recall line from dirty PE (cache state to shared); update memory; turn dirty-bit OFF; turn p[i] ON; supply recalled data to PE-i; } Write to main memory: If dirty-bit OFF then { send invalidations to all PEs caching that block; turn dirty-bit ON; turn P[i] ON; ... } ...

Directory Protocol Messages Message type Source Destination Msg Content Read miss Local cache Home directory P, A Processor P reads data at address A; make P a read sharer and arrange to send data back Write miss Local cache Home directory P, A Processor P writes data at address A; make P the exclusive owner and arrange to send data back Invalidate Home directory Remote caches A Invalidate a shared copy at address A. Fetch Home directory Remote cache A Fetch the block at address A and send it to its home directory Fetch/Invalidate Home directory Remote cache A Fetch the block at address A and send it to its home directory; invalidate the block in the cache Data value reply Home directory Local cache Data Return a data value from the home memory (read miss response) Data write-back Remote cache Home directory A, Data Write-back a data value for address A (invalidate response)

State Transition Diagram for an Individual Cache Block in a Directory Based System States identical to snoopy case; transactions very similar. Transitions caused by read misses, write misses, invalidates, data fetch requests Generates read miss & write miss msg to home directory. Write misses that were broadcast on the bus for snooping => explicit invalidate & data fetch requests. Note: on a write, a cache block is bigger, so need to read the full cache block

CPU -Cache State Machine CPU Read hit State machine for CPU requests for each memory block Invalid state if in memory Invalidate Shared (read/only) Invalid CPU Read Send Read Miss message CPU read miss: Send Read Miss CPU Write: Send Write Miss msg to h.d. CPU Write:Send Write Miss message to home directory Fetch/Invalidate send Data Write Back message to home directory Fetch: send Data Write Back message to home directory Invalid: read => shared write => dirty shared looks the same CPU read miss: send Data Write Back message and read miss to home directory Exclusive (read/writ) CPU read hit CPU write hit CPU write miss: send Data Write Back message and Write Miss to home directory

State Transition Diagram for the Directory Same states & structure as the transition diagram for an individual cache 2 actions: update of directory state & send msgs to satisfy requests Tracks all copies of memory block. Also indicates an action that updates the sharing set, Sharers, as well as sending a message.

Directory State Machine Read miss: Sharers += {P}; send Data Value Reply State machine for Directory requests for each memory block Uncached state if in memory Read miss: Sharers = {P} send Data Value Reply Shared (read only) Uncached Write Miss: Sharers = {P}; send Data Value Reply msg Write Miss: send Invalidate to Sharers; then Sharers = {P}; send Data Value Reply msg Data Write Back: Sharers = {} (Write back block) Invalid: read => shared write => dirty shared looks the same Write Miss: Sharers = {P}; send Fetch/Invalidate; send Data Value Reply msg to remote cache Read miss: Sharers += {P}; send Fetch; send Data Value Reply msg to remote cache (Write back block) Exclusive (read/writ)

Example Directory Protocol Message sent to directory causes two actions: Update the directory More messages to satisfy request Block is in Uncached state: the copy in memory is the current value; only possible requests for that block are: Read miss: requesting processor sent data from memory & requestor made only sharing node; state of block made Shared. Write miss: requesting processor is sent the value & becomes the Sharing node. The block is made Exclusive to indicate that the only valid copy is cached. Sharers indicates the identity of the owner. Block is Shared => the memory value is up-to-date: Read miss: requesting processor is sent back the data from memory & requesting processor is added to the sharing set. Write miss: requesting processor is sent the value. All processors in the set Sharers are sent invalidate messages, & Sharers is set to identity of requesting processor. The state of the block is made Exclusive.

Example Directory Protocol Block is Exclusive: current value of the block is held in the cache of the processor identified by the set Sharers (the owner) => three possible directory requests: Read miss: owner processor sent data fetch message, causing state of block in owner’s cache to transition to Shared and causes owner to send data to directory, where it is written to memory & sent back to requesting processor. Identity of requesting processor is added to set Sharers, which still contains the identity of the processor that was the owner (since it still has a readable copy). State is shared. Data write-back: owner processor is replacing the block and hence must write it back, making memory copy up-to-date (the home directory essentially becomes the owner), the block is now Uncached, and the Sharer set is empty. Write miss: block has a new owner. A message is sent to old owner causing the cache to send the value of the block to the directory from which it is sent to the requesting processor, which becomes the new owner. Sharers is set to identity of new owner, and state of block is made Exclusive.

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 A1 and A2 map to the same cache block

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 A1 and A2 map to the same cache block

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 A1 and A2 map to the same cache block

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 Write Back A1 and A2 map to the same cache block

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 A1 and A2 map to the same cache block

Example Processor 1 Processor 2 Interconnect Directory Memory P2: Write 20 to A1 A1 and A2 map to the same cache block

Multiprocessors Snooping vs. Directory Useful for smaller systems Send all requests for data to all processors Processors snoop to see if they have a copy and respond accordingly Requires broadcast, since caching information is at processors Works well with bus (natural broadcast medium) But, scaling limited by cache miss & write traffic saturating bus Dominates for small scale machines (most of the market) Directory-based schemes Scalable multiprocessor solution Keep track of what is being shared in a directory Distributed memory → distributed directory (avoids bottlenecks) Send point-to-point requests to processors