SpecC and SpecCharts Reviewed and Presented by Heemin Park and Eric Kwan EE202A - Fall 2001 Professor Mani Srivastava.

Slides:



Advertisements
Similar presentations
Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine.
Advertisements

Embedded System, A Brief Introduction
SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid ELECT 1002 Spring 2008 System-On-a-Chip Design.
Copyright  2003 Dan Gajski and Lukai Cai 1 Transaction Level Modeling: An Overview Daniel Gajski Lukai Cai Center for Embedded Computer Systems University.
© 2004 Wayne Wolf Topics Task-level partitioning. Hardware/software partitioning.  Bus-based systems.
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
ECE Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)
2-Hardware Design of Embedded Processors (cont.) Advanced Approaches.
Give qualifications of instructors: DAP
The System and Software Development Process Instructor: Dr. Hany H. Ammar Dept. of Computer Science and Electrical Engineering, WVU.
Ch 3 System Development Environment
Evolution and History of Programming Languages Software/Hardware/System.
The Concept of Computer Architecture
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Introductory Comments Regarding Hardware Description Languages.
1 HW/SW Partitioning Embedded Systems Design. 2 Hardware/Software Codesign “Exploration of the system design space formed by combinations of hardware.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
Source Code Optimization and Profiling of Energy Consumption in Embedded System Simunic, T.; Benini, L.; De Micheli, G.; Hans, M.; Proceedings on The 13th.
Spec-C, Handel-C, SystemC : A Comparative Study By: Nikola Rank 13 March 2006.
Copyright  1999 Daniel D. Gajski IP – Based Design Methodology Daniel D. Gajski University of California
Modeling State-Dependent Objects Using Colored Petri Nets
Joshua GarrettUniversity of California, Berkeley SpecCharts: A VHDL Front-End for Embedded Systems.
Transaction Level Modeling Definitions and Approximations Trevor Meyerowitz EE290A Presentation May 12, 2005.
Codesign Framework Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available in their web.
Mahapatra-Texas A&M-Fall'001 Codesign Framework Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available.
Real-Time System Requirements & Design Specs Shaw - Chapters 3 & 4 Homework #2: 3.3.1, 3.4.1, Add Error states to Fig 4.1 Lecture 4/17.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
1 System-Level Description Languages Andrew Mihal EE249 Fall 1999 Project Presentation 4 December 1999.
1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.
(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
Ch.2 Part A: Requirements, State Charts EECE **** Embedded System Design.
Roza Ghamari Bogazici University April Outline Introduction SystemC Language Formal Verification Techniques for SystemC Design and Verification.
Using Mathematica for modeling, simulation and property checking of hardware systems Ghiath AL SAMMANE VDS group : Verification & Modeling of Digital systems.
1 5-High-Performance Embedded Systems using Concurrent Process (cont.)
Chap. 1 Overview of Digital Design with Verilog. 2 Overview of Digital Design with Verilog HDL Evolution of computer aided digital circuit design Emergence.
CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {
Extreme Makeover for EDA Industry
System Design with CoWare N2C - Overview. 2 Agenda q Overview –CoWare background and focus –Understanding current design flows –CoWare technology overview.
Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
- 1 - EE898_HW/SW Partitioning Hardware/software partitioning  Functionality to be implemented in software or in hardware? No need to consider special.
The System and Software Development Process Instructor: Dr. Hany H. Ammar Dept. of Computer Science and Electrical Engineering, WVU.
SpecC stands for “specification description language based on C”.
MILAN: Technical Overview October 2, 2002 Akos Ledeczi MILAN Workshop Institute for Software Integrated.
Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.
CprE 588 Embedded Computer Systems Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #5 – System-Level.
M.Mohajjel. Digital Systems Advantages Ease of design Reproducibility of results Noise immunity Ease of Integration Disadvantages The real world is analog.
© 2006 Pearson Addison-Wesley. All rights reserved 2-1 Chapter 2 Principles of Programming & Software Engineering.
Architecture Analysis and Design Language: An Overview Drew Gardner.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Chapter 11: System Design.
ECE 587 Hardware/Software Co- Design Lecture 23 LLVM and xPilot Professor Jia Wang Department of Electrical and Computer Engineering Illinois Institute.
1 5-High-Performance Embedded Systems using Concurrent Process (cont.)
Winter-Spring 2001Codesign of Embedded Systems1 Essential Issues in Codesign: Models Part of HW/SW Codesign of Embedded Systems Course (CE )
System-on-Chip Design
Digital System Design An Introduction to Verilog® HDL
Behavioral Style Combinational Design with VHDL
VLSI Testing Lecture 5: Logic Simulation
VLSI Testing Lecture 5: Logic Simulation
2-Hardware Design of Embedded Processors (cont.)
IP – Based Design Methodology
Design Flow System Level
Retargetable Model-Based Code Generation in Ptolemy II
CoCentirc System Studio (CCSS) by
Hardware Description Languages
Embedded systems, Lab 1: notes
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
Transaction Level Modeling: An Overview
Essential Issues in Codesign: Models
Digital Designs – What does it take
Presentation transcript:

SpecC and SpecCharts Reviewed and Presented by Heemin Park and Eric Kwan EE202A - Fall 2001 Professor Mani Srivastava

Overview Current problems in embedded systems development The solution – SpecC / SpecCharts Key feature: Program State Machine Highlight of SpecC Conclusion Questions

Current Design Problem Prototype debugging occupy 43% of development time Miscommunication of requirement Ambiguous specifications Absence of simulation and synthesis tool  HUGE design loop The reason – lack of a proper specification language Planning Specification Implementation Prototype Verification BIG LOOP!!

The solution: SpecC & SpecCharts Avoid miscommunication of requirement and incomplete / ambiguous specifications Proper specifications reduce debugging time by 29% Allow development of synthesis and simulation tools Simulate without building a prototype Planning Specification Implementation Prototype Performance Evaluation Rapid Prototyping AGILE DESIGN

Design Flow using SpecC Bus- functional Structural System design Specification model Algor. IP Proto. IP Architecture model Communication synthesis Communication model Comp. IP Implementation model Software compilation Interface synthesis Hardware synthesis Backend RTOS IP RTL IP Architecture exploration Capture Timed (estimated) RTL/IS Cycle- accurate Functional Structure / Implementation detail Untimed (causality) Order / Timing detail Timing- accurate SpecC

Properties of embedded System VHDL support the following behavior of embedded systems: Behavior Decomposition (Partial) Sequential Algorithm Behavior Completion (Partial) Not supported: State Transition Exceptions

Why did others failed? CharacteristicSpecChartsSpecCVHDLVerilogEsteral State Charts Behavioral decomposition Yes PartialYes State TransitionYes No Yes ExceptionYes NoYes Sequential algorithm Yes PartialNo Behavioral completion Yes PartialYes No

SpecCharts and SpecC Same Idea, different implementation SpecCharts is an extension to VHDL to tailored for embedded system design SpecC – ” specification description language based on C ” Both implement the idea of a Program State Machine (PSM)

Program State Machine(PSM) Hierarchical/Concurrent FSM + Programming language Program-state(PS) Status Inactive Executing Complete Computation Leaf Concurrent Sequential conditional transition arcs on completion or immediately

Program State Machine(Cont) SpecCharts PS described by procedures based on VHDL SpecC PS described by procedures in a programming language based on C PS4 PS5 PS3 PS2 PS1... a = 42; while (a<100) { b = b + a; if (b > 50) c = c + d; else c = c + e; a = c; }... PSM model Sequential Leaf Concurrent

SpecChart Descriptions Transition immediately(TI) (starts from boundary) Transition on Complete(TOC) Complete state behavior CheckCode type leaf is begin code_ok <= true; for (i in 1 to 4) loop wait until tone /= “1111” and tone’event; if (tone /= user_code(i)) then code_on <= false; end if; end loop; end; Textual-versionGraphical-version Initial state RemoteOperation code_ok=‘0’ hangup=‘1’ code_ok=‘1’ RespondToCmds CheckCode

Design Flow using SpecCharts VHDL Simulator SpecCharts to VHDL translator VHDL Synthesizer VHDL Verification tool VHDL Codes SpecChart Descriptions

The SpecC Model Traditional model Processes and signals Mixture of computation and communication Automatic replacement impossible SpecC model Behaviors and channels Separation of computation and communication Plug-and-play s2 s1 s3 P1P2 B2 v2 v1 v3 B1 C1

The SpecC Language ANSI-C Program is set of functions Execution starts from function main() SpecC Foundation: ANSI-C Program is set of behaviors, channels, and interfaces Execution starts from behavior Main.main() /* HelloWorld.c */ #include void main(void) { printf(“Hello World!\n”); } // HelloWorld.sc #include behavior Main { void main(void) { printf(“Hello World!\n”); } };

The SpecC Language Basic structure Top behavior Child behaviors Channels Interfaces Variables (wires) Ports b1b2 v1 c1 B p1p2 Behavior Ports Interfaces Channel Variable (wire) Child behaviors

The SpecC Language Basic structure interface I1 { bit[63:0] Read(void); void Write(bit[63:0]); }; channel C1 implements I1; behavior B1(in int, I1, out int); behavior B(in int p1, out int p2) { int v1; C1 c1; B1 b1(p1, c1, v1), b2(v1, c1, p2); void main(void) { par { b1.main(); b2.main(); } }; b1b2 v1 c1 B p1p2

behavior B_pipe { B b1, b2, b3; void main(void) {pipe{b1.main(); b2.main(); b3.main(); } } }; The SpecC Language Behavioral hierarchy B_par b1 b3 b2 B_seq b1 b3 b2 B_fsm b1 b3 b2 b5b6 b4 B_pipe b1 b3 b2 behavior B_seq { B b1, b2, b3; void main(void) { b1.main(); b2.main(); b3.main(); } }; behavior B_fsm { B b1, b2, b3, b4, b5, b6; void main(void) { fsm { b1:{…} b2:{…} …} } }; behavior B_par { B b1, b2, b3; void main(void) { par{b1.main(); b2.main(); b3.main(); } } }; Sequential execution FSM execution Concurrent execution Pipelined execution

Design Flow using SpecC Bus- functional Structural System design Specification model Algor. IP Proto. IP Architecture model Communication synthesis Communication model Comp. IP Implementation model Software compilation Interface synthesis Hardware synthesis Backend RTOS IP RTL IP Architecture exploration Capture Timed (estimated) RTL/IS Cycle- accurate Functional Structure / Implementation detail Untimed (causality) Order / Timing detail Timing- accurate SpecC

Conclusion SpecCharts PSM: model of computation for embedded system VHDL base: limited support for embedded software SpecC Well-known high-level language with support of PSM Design environment still developing Architecture exploration, refinement, communication synthesis,

Questions…

References Literature Vahid, F.; Narayan, S.; Gajski, D.D. SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. on CAD, Vol.14(No.6), June Pp SpecC: Specification Language and Methodology, by Gajski, Zhu, D ö mer, Gerstlauer, Zhao, Kluwer Academic Publishers, Circuits and Systems, 2001, Tutorial Guide: ISCAS 2001, The IEEE International The SpecC Language, pp.5.1_1-5.1_12. Modeling and Design with SpecC, pp.5.2_1-5.2_12. SpecC Design Environment, pp.5.6_1-5.6_4. SpecC Open Technology Consortium, pp.5.7_1-5.7_5. Online SpecC web pages at UCI SpecC Open Technology Consortium (STOC)