Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B.

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Presentation transcript:

Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B

2 Electrical and Computer Engineering Board Demonstration

3 Electrical and Computer Engineering Build Process  Board Assembly  Verilog Programming Plan State Machine Synthesis Simulation Burning the Program  Testing MIDI-OX GoLogic Logic Analyzer

4 Electrical and Computer Engineering Board Assembly  No “correct layout”  Easy way vs. hard way Plan ahead Practice neat wiring Check electrical connections Double check the schematic Test using multimeter

5 Electrical and Computer Engineering Verilog Synthesis  Use the full compile option when synthesizing  Check warnings if your design does not work Some harmless, some indicate major issues.  State machine viewer, RTL viewer Good for checking overall design RTL viewer more useful for designs with multiple modules

6 Electrical and Computer Engineering Waveform Simulation  Simulate design using Vector Waveform Files Add inputs pins to your waveform, create input signals Add outputs and internal registers to “watch” values Modify simulation settings (under “Assignments”) to specify a simulation length.  Make sure your design simulates properly before moving on!

7 Electrical and Computer Engineering Programming the CPLD  Two options Dedicated programmer Altera USB ByteBlaster (JTAG) ‏  Quartus interface After Verilog is synthesized and programmer connected tools -> programmer -> select program and verify then click start Check Quartus output to confirm programming succeeded

8 Electrical and Computer Engineering Testing with MIDI-OX  Set up Yamaha UX16 as output device in MIDI-OX  Use keyboard input to send notes to breadboard  Confirm number on board agrees with played note

9 Electrical and Computer Engineering GoLogic Logic Analyzer  Settings Make sure to set a proper sampling rate Set up a trigger based on incoming MIDI signal Modify pre-store settings  Examine MIDI protocol Confirm output of the MIDI-OX Confirm clock signal  Not critical for this lab Still good practice

10 Electrical and Computer Engineering Pitfalls and How to Avoid Them  Breadboarding Bad connections Miswired parts (Have everyone in your team check) Dead chips  MIDI-OX Simultaneous notes  Verilog/Quartus Confirm Quartus pin layout agrees with board Poor programming style can lead to mismatch between simulation and device behavior Take time to understand blocking/non-blocking, and plan out how you are going to structure your program.

11 Electrical and Computer Engineering Quartus II Misc.  Create new Project Page 1: Name Appropriately Page 2: Nothing Page 3: Change Family and Name as given in lecture Page 4/5: Nothing  File -> new -> Verilog HDL file  Start Compilation – Purple arrow  Assignments -> Pins Make sure you have rite chip, set on Page 3 Click and drop I/O to pins, close re-compile.  Tools -> Programmer Check connection/settings, click start wait for 100%

12 Electrical and Computer Engineering General Advice  Start early. Plan before you start.  Don't panic if it doesn't work the first time! Simulate a complete MIDI message in Quartus Check breadboard wiring Confirm the CPLD is working properly with a test program  Reference lecture slides on Verilog frequently. Use template Correctly segregate sequential and combinational parts  Google and Wikipedia are your friend Understand the MIDI protocol Learn from Verilog and Quartus examples