Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Performance analysis of sequential machines.

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Presentation transcript:

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Performance analysis of sequential machines.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Unbalanced delays Logic with unbalanced delays leads to inefficient use of logic: long clock periodshort clock period

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Signal skew Machine data signals must obey setup and hold times—avoid signal skew.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew Clock must arrive at all memory elements in time to load data.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Qualified clocks and skew n Logic in the clocking path introduces delay. n Delay can cause clock to arrive at latches at different times, violating clocking assumptions. n When designing qualification logic: –minimize and check skew; –sharpen clock edge.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Qualification skew example

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock period n For each phase, phase period must be longer than sum of: –combinational delay; –latch propagation delay. n Phase period depends on longest path.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Unbalanced delays Logic with unbalanced delays leads to inefficient use of logic: long clock periodshort clock period

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Flip-flop-based system performance analysis

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Flip-flop-based system model n Clock signal is perfect (no rise/fall), period P. n Clock event on rising edge. n Setup time s. –Time from arrival of combinational logic event to clock event. n Propagation time p. –Time for value to go from flip-flop input to output. n Worst-case combinational delay C. –Time from output of flip-flop to input.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock parameters

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock period constraint n P >= C + s + p. s p C

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock with rise/fall

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Rise/fall clock period constraint n P >= C + s + p + t r. s p C trtr

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Min-max delays n Delays may vary: –Manufacturing variations. –Temperature variations. n Min/max delays compound over paths. –Delays within a chip are correlated. t

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Latch system clock period n For each phase, phase period must be longer than sum of: –combinational delay; –latch propagation delay. n Phase period depends on longest path.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Latch-based system model

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Two-phase timing parameters

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock period constraint n Total clock period (both phases): –P >= C1 + C2 + 2s + 2p. n Each phase must meet timing for its own latch.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Latch-based system model

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Advanced performance analysis n Latch-based systems always have some idle logic. n Can increase performance by blurring phase boundaries. Results in cycle time closer to average of phases.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Example with unbalanced phases One phase is much longer than the other:

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Spreading out a phase Compute only part of long paths in one phase:

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Spreading out a phase, cont’d. Use other phase for end of long logic block and all of short logic block:

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Problems n Hard to debug—can’t stop the system. n Hard to initialize system state. n More sensitive to process variations.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Timing and glitches in FSMs n If inputs don’t change, can outputs glitch? DQ logic input output

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Skew n Skew: relative delay between events. n Signal skew: most important for asynchronous, timing-dependent logic. n Clock skew: can harm any sequential system.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Signal skew Machine data signals must obey setup and hold times—avoid signal skew.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Signal skew example

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew Clock must arrive at all memory elements in time to load data.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew example

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew in system DQDQ logic 

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew and qualified clocks

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew analysis model s 12 =  1 –  2 s 21 =  2 –  1

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Skew and clock period n Assume that each flip-flop operates instantaneously: –T >=  2 +  12 n If clock arrives at FF2 after FF1, then we have more time to compute. n Given clock period, determine allowable skew: –s 12 >= T +  2

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Timing through logic n As skew increases, we have less time to get the signal through the logic.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock distribution n Often one of the hardest problems in clock design. –Fast edges. –Minimum skew.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Clock skew example 10 ps 20 ps 30 ps DQDQDQ DQ

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Retiming Retiming moves registers through combinational logic:

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Retiming properties n Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic. n Retiming may increase number of registers required. n Retiming must preserve number of registers around a cycle—may not be possible with reconvergent fanout.