Electrical Data Transmission on Flex Cables at 320 Mbps Peter Manning, Vitaliy Fadeyev, Jason Nielsen Santa Cruz Institute for Particle Physics University of California, Santa Cruz ATLAS SCT Upgrade meeting at UCSC 12 August 2008 Options and Issues with Optical Transmission Jingbo Ye et al SMU

2008/08/12V. Fadeyev (UCSC)2 Outline Investigating LVDS transmission on flex cable stripline at speeds up to 320 Mbps over cm Results at waveform (eye diagram) level currently. Investigation of different loads and trace geometry. Making modeling more realistic: BERT and latching circuits Optical transmission work: –Demo link status –LOC2 status –Fiber irradiation tests

2008/08/12V. Fadeyev (UCSC)3 Testing Hardware Setup Xilinx ML-310 (Virtex 2 Pro) National DS25BR100EVK

2008/08/12V. Fadeyev (UCSC)4 Prototype Stave Cable Bond to straight traces on cable edge Shields top and bottom bonded together Thanks to Carl, an early version of SCT stave. –50 cm long stripline –Taps every 10 cm

2008/08/12V. Fadeyev (UCSC)5 Assumptions Recall from architecture: we are planning for point- to-point transmission for data, and multiple “tap points” for the clock distribution. Investigation with DPO scope (500 MHz)

2008/08/12V. Fadeyev (UCSC)6 Investigated Trace geometry effects 100 mum wide, 100 mum sep, straight 100 mum wide, 1000 mum sep, straight 100 mum wide, 100 mum sep, zigzag ~300 mum wide, 100 mum sep, zigzag Pt-to-pt PRBS OK X Pt-to-pt CLK OK Pt-to-pt PRBS; 4 taps of 2 pF XX Pt-to-pt CLK; 4 taps of 2 pF OK Pt-to-pt CLK; 4 taps of 10 pF X Pt-to-pt PRBS; 4 taps of repeater (0.6 pF) OK Pt-to-pt CLK; 4 taps of repeater (0.6 pF) OK Pt-to-pt PRBS; 4 pF at source OK The studied cable has a several types of striplines.

2008/08/12V. Fadeyev (UCSC)7 Eye Diagram Examples Clock at the receiver with 4 x 2pF loads along the stripline Eye diagram at the receiver with 4 x SN65LVDS100 receiver loads along the stripline

2008/08/12V. Fadeyev (UCSC)8 Cross-Talk Measure cross-talk signal on adjacent terminated trace (orange) separated by 100 microns (same as stripline width) Drive differential pair with 100 MHz clock (blue) Note different scales: cross-talk amplitude is less than 5%. At source endAt termination end

2008/08/12V. Fadeyev (UCSC)9 BERT Development Need an error rate tester for quantitative assessment of transmission quality. Have a basic structure for bit-level investigation; studying phase control …stream at 280 MHz Data in Error out Inv. Data in (=>360 deg. delay) Error out 10101…stream at 320 MHz

2008/08/12V. Fadeyev (UCSC)10 Hybrid “Models” Looked at a couple of circuits that could latch the data wrt input clock, thereby modeling the data acceptance by module (and stave?) controllers. OnSemi’s DFF MC10EP52OnSemi’s DFF NBSG53A

2008/08/12V. Fadeyev (UCSC)11 Conclusions Indications for satisfactory performance for several variations of stripline geometry. For multi-tap scenario, the performance depends on “tap” loads. Cross-talk between nearby traces is small. Making progress with BERT and hybrid “models”

2008/08/12V. Fadeyev (UCSC)12 Next Steps and Time Table Finish BERT firmware development, measure error rates ~3 months Follow up with software modeling ~2 months Instrument Carl’s long ladder and measure the performance (place multiple hybrids or “models” with realistic multi-tap clock distribution etc and measure individual line error rates) ~3 months To complete these near-term tasks we’d need 6-9 months, depending on degree of parallelism practically achievable. Custom-made cables with proper routing? Serial powering and effect of balancing the protocols?

Demo Link and the LOC Status Report (This is a shortened version of the report. The full version is available on the meeting ’ s web site.) 1.Demo Link status 2.LOC2 status 3.Irradiation tests on optical fiber 4.Summary Vitaliy for the SMU team

Reminder: GOL, LOC, GBT … H1 H2H3H4…. SC Serialized data It is envisoned that at the end of the stave there is a stave controller chip which serializes the data from hybrids, accepts commands and broadcasts them (phase delayed) to module controllers, etc. There are several ASICs with overlapping functionalities: GOL – Gygabit Optical Link (CERN), a serializer in existence. 40 MHz -> 0.8 (1.6) GHz. GBT – Gygabit Bydirectional Trigger and data link (CERN), in development, multipurpose. >2.5 GHz data bandwidth. LOC – Link On a Chip (SMU), in development, serializer, ~5 GHz bandwidth.

2008/08/12V. Fadeyev (UCSC)15 Demo Link status The idea: –Use the GOL to construct an optical link to read out the staves under development. –Provide a Giga-bit optical link that develops together with the detector and front-end ASICs. –Provide a test vehicle to study system and integration issues at an early stage. –Demo Links can be quickly constructed with LOC or GBTx when they become available in 2009/2010. –These demo links will lead a baseline design for final production, installation evaluations and will provide links for reliability studies before the production begins. The status: –Next page. The plan:

2008/08/12V. Fadeyev (UCSC)16 The plan: –Currently layout the two interface boards. –FPGA code development when all boards are out for fabrication and assembly. –8/25 – 9/5: debugging at SMU. –9/10, 11: first test at LBNL. –May need a few integration tests and modifications of the interface boards. –Will provide boards to interested groups for system level studies by the end of this year.

2008/08/12V. Fadeyev (UCSC)17 LOC2 status Design status: –Currently carry out post layout simulations on key components to define the speed of LOC2. –Still in discussion with people in Inner Detector and in LAr trying to make LOC2 best fit the needs in both readout. In ID, we need to work more closely with people who develop the (supper-) module-controller to understand the input to LOC2. We may make use of the fact that the output of MC is already 8B/10B encoded to maximize the use of the bandwidth. –Current simulations show a 5 Gbps LOC2 hopeful. –Details in the following pages. The plan: –after the status report.

2008/08/12V. Fadeyev (UCSC)18 LOC2 Block diagram and challenging spots: 16 bit Input register LVDS to LVCMOS 2:1 MUX to 8 bit 8B/10B Comma PRBS PLL + clks MUX Cntrl config Odd bits shift register Even bits shift register Latch CML driver 2:1 MUX Data Clk_ref Cntrl/Config 16 LVDS 10 bit Serial output to Versatile Link Critical components: 1.PLL. VCO, the first stage divider  speed. Architecture choice: reliability, jitter, implementation. 2.Static D-flip-flop. The building block of the divider, and the shift register  speed. 3.CML driver. Inverter: basic unit of a CMOS circuit. Study the PMOS/NMOS ratio, circuit speed. We may move the 8B/10B encoder out of LOC2 to better interface ID and LAr. That is, we may design dedicated interface chips for LOC’s applications. This is in discussion right now and will be finalized soon.

2008/08/12V. Fadeyev (UCSC)19 LOC2 work plan, near future Finalize the structure: with 8B/10B encoder or move the encoder out. With the latter, dedicated interface chips will be designed to best cope with the input data and maximize the use of the link bandwidth. Post layout studies on all the critical components and understand the speed of LOC2. At this moment, 5 Gbps is hopeful. Careful studies on the PLL, mostly the RJ, or phase noise. A design review (1 st ), Oct./Nov. time frame, at BNL or CERN on the critical parts. Get help from the community on things we may have overlooked, misunderstand, etc.

2008/08/12V. Fadeyev (UCSC)20 LOC2 work plan, till April 2009 After the 1 st design review, we will move on to –Complete PLL and clock unit design. –Complete the serializer design. –Implement the 8B/10B and 64B/66B Encoders, or design the interface chips. –Implement the control/config unit. –Implement the CML driver. We aim for the 2 nd design review, Jan./Feb. 2009, on the whole chip or chip set. We aim for the April 09 submission, and the tests in lab July 09. We will provide demo-link and system design document for groups that are interested in using this chip in the fall of Full evaluation of LOC2, including irradiation tests are planned to take place in the fall of Reference: GBTx is planned to be available end of 2009.

2008/08/12V. Fadeyev (UCSC)21 Irradiation tests on optical fiber To complete a rad-tol optical link system, one needs to identify rad-tol components such as VCSEL, fiber and PINs. This part of the work is now the Versatile Project. At SMU, we identified a 10G fiber and performed several tests on the fiber. The report here consists: –Results from ATLAS LAr. –Narrow down to Germanium doped GRIN fiber. –Preliminary tests.

2008/08/12V. Fadeyev (UCSC)22 Preliminary tests Gamma (Co-60) and Proton (230 MeV) tests Infinicor SX+ 50/250  m/1.6mm MM. 10G fiber from Corning. Germanium doped. Very small light loss at low flux (dose rate). Big loss at high flux but anneals very quickly (within 1 hour) back. Fiber under proton test

2008/08/12V. Fadeyev (UCSC)23 Preliminary tests Co-60 at BNL, dose rate: 30 krad/hr. Fiber: Corning Infinicor SX+ 50/125 MM fiber, 45 m under irradiation. Total RIA: 0.04 dB/m after 1.4 Mrad. Annealing effects observed. More annealing results will follow once we get our equipment back to SMU. Run #Dose (krad) Accumulated dose (krad)fibre RIA (dB) Accumulated RIA (dB) Ref. fiber (dB) Accumulated ref. fiber (dB)

2008/08/12V. Fadeyev (UCSC)24 Conclusion on fiber (preliminary) Corning Infinicor SX+ 50/125 MM fibers from different production batches, packaging companies were irradiated with gamma (Co-60) and proton (230 MeV). More tests with higher dose rate and total dose are to be carried out by Oxford group to reach 50 Mrads. Careful data analysis, especially on annealing effects, needs to be carried out. More tests, especially neutron or proton may be needed to study possible NIEL effect, or to confirm that the lack of it. Preliminary results indicate that this fiber may be suitable for ID upgrade.

2008/08/12V. Fadeyev (UCSC)25 Summary The GOL based demo link will be constructed and put to use in Sept./Oct. time frame. This demo link will be used to perform many system level studies on the Giga-bit optical link. Demo links based on LOC or GBTx will follow. This exercise will lead to a baseline design for the upgrade of optical readout. The LOC2 design is on track for a user chip in It is hopeful to achieve 5 Gbps speed. We need to work more closely with upstream ASIC developers to define the interface. R&D work in the frame of Versatile Link project is on-going to identify components for a rad-tol optical link. At least one type of fiber (Corning Infinicor SX+ 50/125 MM ) has been tested with gamma and proton and the preliminary results indicate that this fiber may be suitable for the ID upgrade.

2008/08/12V. Fadeyev (UCSC)26 Backup Slides

2008/08/12V. Fadeyev (UCSC)27 Effect of the Tap Put 10 pF load at the source in two ways: 1) serially 2) via 2 cm long tap. Serial insertionWith 2 cm long tap

2008/08/12V. Fadeyev (UCSC)28 Eye Diagrams with 4 x 2 pF loads Straight traceZigzag trace Worst cases are near the source (tap 1).