256 channel data acquisition system for VISTA focal plane to readout sixteen 2k x 2k Raytheon VIRGO detectors Largest ever such system Leander H. Mehrgan.

Slides:



Advertisements
Similar presentations
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
Advertisements

Controller Tests Stephen Kaye Controller Test Motivation Testing the controller before the next generation helps to shake out any remaining.
Engineer Training XL1200 Electronics. Engineer Training XL1200 Electronics Confidential 2 XL1200 Electronics The XL Jet Electronic System consists of.
256 channel data acquisition system for VISTA focal plane to readout sixteen 2k x 2k VIRGO detectors Largest ever such system.
EML 2023 – Motor Control Lecture 4 – DAQ and Motor Controller.
ESODAC Study for a new ESO Detector Array Controller.
Overview of the current TDR system Introduction Electronics for instrumentation TDR core : Metronome, ADC, Merge Data Handling Pete Jones, University of.
2D Detectors DAQ Overview 2D detectors are organized as tiles providing 10G Ethernet serialized portions of the full.
Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France 24 February 2003 News about SPECS system  SPECS system  SPECS-SLAVE chip  SPECS-SLAVE.
04/02/2004 az Outer Tracker Distribution Boxes 1 EFNI H K Outer Tracker Distribution Boxes Ad Berkien Tom Sluijk Albert Zwart.
20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
Ionization Profile Monitor Front End (IFE) System Presenter: Kwame Bowie PPD/EED Phone: (630)
SDW TAORMINA A NEW GENERATION OF DATA AND CONTROL INTERFACES FOR DIGITAL DETECTORS F. Bortoletto 1, M. D’Alessandro 1, E. Giro 1, R. Cosentino 2,
LarTPC Electronics Meeting Current Work at MSU Fermilab Dan Edmunds 23-February-2010.
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
Manfred Meyer & IDT & ODT 15 Okt Detectors for Astronomy 2009, ESO Garching, Okt Detector Data Acquisition Hardware Designs.
ELI: Electronic Timing System (ETS) at Facility Level E L I – B L – – P R E – B.
DES Collaboration Meeting, Chicago, December 11-13, 2006 T. Shaw1 DES Collaboration Meeting Front End Electronics Status T. Shaw, D. Huffman, M. Kozlovsky,
Engineer Training Electronic System Overview. Engineer Training XL1500 Electronics Confidential 2 XLjet Electronics The XL1500 Electronic System consists.
The Train Builder Data Acquisition System for the European-XFEL John Coughlan, Chris Day, Senerath Galagedera and Rob Halsall STFC Rutherford Appleton.
Introduction to Computers Personal Computing 10. What is a computer? Electronic device Performs instructions in a program Performs four functions –Accepts.
A. Homs, BLISS Day Out – 15 Jan 2007 CCD detectors: spying with the Espia D. Fernandez A. Homs M. Perez C. Guilloud M. Papillon V. Rey V. A. Sole.
SciMeasure Wavefront Sensor Cameras and their Application in the 5m Palomar Adaptive Optics System SciMeasure Analytical Systems, Inc. Ray DuVarney, Charlie.
Online Systems Status Review of requirements System configuration Current acquisitions Next steps... Upgrade Meeting 4-Sep-1997 Stu Fuess.
Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.
AMICA Antarctic Multiband Infrared CAmera Favio Bortoletto INAF – Osservatorio Astronomico di Padova on behalf of the AMICA collaboration Telescope and.
Computer Systems TexPREP Summer Camp Computer Science.
Understanding Data Acquisition System for N- XYTER.
IUCAA FOCAL PLANE ARRAY CONTROLLER (IFPAC) Inter-University Centre for Astronomy and Astrophysics, Pune, INDIA Virtex-5 FPGAEthernet / RocketIO via SFP.
Figure 1: ICD Single Channel Block Diagram Schematic PMT High Voltage Supply (see Figure 4 & 4a) LED Pulser PMT Calibration (see Figure 6) ICD Scintillator.
Computer Components – Unit 2. By Rachel Fiveash..
A Front End and Readout System for PET Overview: –Requirements –Block Diagram –Details William W. Moses Lawrence Berkeley National Laboratory Department.
11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.
Frank Lemke DPG Frühjahrstagung 2010 Time synchronization and measurements of a hierarchical DAQ network DPG Conference Bonn 2010 Session: HK 70.3 University.
The BUS The Central Communications Network Copyright © Curt Hill.
Updated HBD FEM Diagram Clock Master Clock fanoutADC Optical out Backplane Crate GTM/Ethernet New Daughter card + DCM Test pulse.
December 14, 2006Anuj K. Purwar1 Design proposal for Read Out Card (ROC) Anuj K. Purwar December 14, 2006 Nevis Meeting.
Costas Foudas, The Tracker Interface to TCS, The CMS Silicon Tracker FED Crates What goes in the FED Crates ? What do we do about the VME controller.
HBD electronics status All the ADC and XMIT boards are installed. –Top 3 crates are for the ADC, XMIT boards –Bottom crate is for test pulse boards/future.
PC Internal Components Lesson 4.  Intel is perhaps the most recognizable microprocessor manufacturer. List some others.
A+ Guide to Managing and Maintaining Your PC Fifth Edition Chapter 22 All About SCSI.
Beam diagnostics developments at LAPP: Digital part CTF3 Collaboration Meeting Louis Bellier, Richard Hermel, Yannis Karyotakis, Jean Tassan,
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA.
LIGO-G9900XX-00-M LIGO II1 Why are we here and what are we trying to accomplish? The existing system of cross connects based on terminal blocks and discrete.
Instrument Control Systems Seminar 2014, 20 th -24 th October 2014 Instrument Control Systems 2014 NGC controller Leander Mehrgan.
Electronics Workshop GlueX Collaboration Meeting 28 March 2007 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Physics Division Topics: Review.
Preparations to Install the HBD for Run 6 Craig Woody BNL PHENIX Weekly Meeting January 26, 2006.
Update on the New Developments & Analysis from Hawaii Larry Ruckman & Gary Varner Instrumentation Development Laboratory (ID-Lab) University of Hawaii.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
Vanderbilt University Toshiba IR Test Apparatus Project Final Design Review Ahmad Nazri Fadzal Zamir Izam Nurfazlina Kamaruddin Wan Othman.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
Networks Are you Wired?. Networking A network is defined as two or more computers connected together –Peer-to-peer when a server is not involved. –Client-server.
PCs ENVIRONMENT and PERIPHERALS Lecture 4. An expansion cards: - An expansion card (expansion board) is an electronic circuit board that adds more functionality.
The ALICE TPC Readout Control Unit 10th Workshop on Electronics for LHC and future Experiments 13 – 17 September 2004, BOSTON, USA Carmen González Gutierrez.
INDUSTRIAL SEMINAR ON RDSO : TELECOMMUNICATION DEPARTMENT MADE BY: MAMTA CHAUDHARY
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
LHCb Outer Tracker Electronics 40MHz Upgrade
DAQ read out system Status Report
Readout electronics for aMini-matrix DEPFET detectors
Instrument Control Systems 2014
The Train Builder Data Acquisition System for the European-XFEL
Front-end electronic system for large area photomultipliers readout
VELO readout On detector electronics Off detector electronics to DAQ
Gustavo Rahmer ETS - CTIO
Commodity Flash ADC-FPGA Based Electronics for an
Fiber Based Synchronous Timing System
European Southern Observatory - Instrumentation Division
Digitally subtracted pulse between
Presentation transcript:

256 channel data acquisition system for VISTA focal plane to readout sixteen 2k x 2k Raytheon VIRGO detectors Largest ever such system Leander H. Mehrgan 1), N. Bezawada 2), R. Dorn 1), S. Eschbaumer 1), G. Finger 1), M. Meyer 1), J. Stegmeier 1), G. Woodhouse 3) 1) European Southern Observatory, 2) UK Astronomy Technology Centre, 3) Rutherford Appleton Laboratory

The ESO’s standard Infrared Array Control Electronics, IRACE, is used to control and read out the VISTA focal plane. The IRACE system is modular and has been adapted for VISTA IR camera requirements.

To build up the system, all boards, in total 27, are distributed over three separate racks, 19 inch wide. The main rack, called master rack, contains Clock- and Bias-driver boards, Sequencer, Giga-Link and Sync boards. The other two racks, called slave racks, contain sixteen ADC boards. Each board is accommodating 16 video channels.

Because of the bandwidth limitation of the IRACE-PCI card (up to 65 MB/s) we had to split the backplane into two groups. Each group contains four ADC boards and one Giga-Link board, which capture and transport the data over the fiber optic to the host PCI card.

All three boxes are connected together by digital isolated differential signal cables to distribute the system clock, the convert pulses and some other control signals. In this way we can synchronize all ADC’s without timing jitter and ground loops.

Three Linux PC’s have been used for the whole system. It is a rack mountable PC (double 3 GHz CPUs and 3 Gbytes of memory). One of them is used for the command interface and the other two just for data capturing. One of the Linux PC contains at least three PCI-cards, which are the host interface of the system. Because of the bus structure of the PC motherboard those PCI cards do not need to share the same bus.

At the End: The main reason for the presentation was just to show you the high level of flexibility and modularity of IRACE system. The experience of using IRACE for all instruments at ESO, up to 18, will be used by the ESO’s new common controller NGC.