PDP-8 Jon Andrews Project Outline: To implement a real commercial processor into an Field Programmable Gate Array (FPGA). It should be able to run code from the original processor. Processor: 8080, 6800, 6502, PDP-8 Digital Equipment Corporation PDP-8: 12 Bit CISC Machine 4K Words of Memory 8 Basic Instructions Operating System DEC OS/8 History 100,000 Machines Sold PDP-8/I Introduced in 1968 Last Machine Built In 1984 (PDP-8/A) Jon Andrews Supervisor: J Garside My Little Computer

PDP-8 Jon Andrews Instruction Set Instructions AND, TAD, ISZ, DCA, JMP, JMS, IOT, OP Instruction Set Format: 3 Bits for Opcode 7 Bits for address 12-bit Memory Location is Inferred Key Features Jump to Sub Routine Return Address Stored in 0 Auto Indexing Instruction Set Flow Control (no conditional branch) 13 Microcoded Instructions Page 0 Page 1 Page 31 Page 32 Page Layout 12 Bits

PDP-8 Jon Andrews Example Instruction E.G AT Location Instruction:Two’s Complement ADD Indirect Bit:‘1’ Page Bit:‘1’ Page Offset:‘ ’ EA:( ) = CA:( ) = This will give AC <- AC ADD I Bits

PDP-8 Jon Andrews Processor Operation Original PDP-8 –7 Fetch States –6 Executions States –1 IDLE State –Total 14 States My Implementation –5 Generic States Reasons For Reduction –Larger Transistor Budget –Ability to Operations in Parallel –Faster Memory –More Buses

PDP-8 Jon Andrews State Diagram F0 –Start State –Loop in this state when IDLE F1 –Address of Operand Calculated F2 –Address Read from operand to fetch indirected data E0 –Instruction execution, eg ADD –Loop in this state when microcoded instruction being processed E1 –Updates the Auto Index value of memory F0 F1 F2 E1 E0 Instructions Fetched Get Operand Addr (InDirect) Get Operand (Direct) Get Operand (InDirect) Auto Index Calculation Auto Index Written to Memory (deferred) Get Operand Execution Complete Microcode Incomplete IDLE

PDP-8 Jon Andrews Conclusion Change in design due to technology –Move towards RISC Single Cycle Execution –Register-Register, not Memory –More Functionality now introduced Sub, Multiply Increased performance –Cycle time can be reduced due to the speed of electronics –Execution states dramatically reduced Time Scale Data PathMid Nov ALU + functional blocks End Nov ControlEnd Dec Test ProgramsEnd Feb Time Permitting –I/O Interface –Focal

PDP-8 Jon Andrews Data Path