UMIPS: A Semiconductor IP Repository for IC Design Research and Education Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale and Richard.

Slides:



Advertisements
Similar presentations
SOC Design: From System to Transistor
Advertisements

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Study and Simulation of CMOS LC Oscillator Phase Noise.
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O Borgatti, M. Lertora, F. Foret, B. Cali, L.
Dr. Subbarao Wunnava June 2006 “ Functional Microcontroller Design and Implementation ” Paper Authors : Vivekananda Jayaram Dr. Subbarao Wunnava Research.
Engr. M.K.Debnath1 Microcontroller and PLC Eng. ISRAFIL KHAN. DIPLOMA IN ELECTRONIC.
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock.
VLSI Curriculum Workshop
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale and Richard B. Brown Academic and Professional Resources for Student-Led Technology Ventures.
The IGERT Program Preliminary Proposals June 2008 Carol Van Hartesveldt IGERT Program Director IGERT Program Director.
Open Educational Resources / production workshop / february 2009 Except where otherwise noted, this work is available under a Creative Commons Attribution.
Digital Circuit Simulations Deborah Barnett, Tidehaven High School Tidehaven ISD Dr. Peng Li, Assistant Professor (faculty mentor) Department of Electrical.
Next-generation Chips & Computing with Atoms Igor Markov ACAL / EECS, Univ. of Michigan.
National Science Foundation: Transforming Undergraduate Education in Science, Technology, Engineering, and Mathematics (TUES)
End-to-End Design of Embedded Real-Time Systems Kang G. Shin Real-Time Computing Laboratory EECS Department The University of Michigan Ann Arbor, MI
Automated Tests in NICOS Nightly Control System Alexander Undrus Brookhaven National Laboratory, Upton, NY Software testing is a difficult, time-consuming.
Future of Online Education in USA
Lynette Olson, Assessment & Effectiveness Director & Gary Langer, Associate Vice Chancellor, Office of the Chancellor, Minnesota State Colleges and Universities.
SOC Design Lecture 1 Overview of SOC.
Serving MERLOT on Your Campus Gerry Hanley California State University and MERLOT Seminars on Academic Computing August 7, 2002 Snowmass CO Copyright Gerard.
Growth and Success through Partnering & Outsourcing.
National Institute of Standards and Technology U.S. Department of Commerce TheTechnology Innovation Program (TIP) Standard Presentation of TIP Marc G.
United Nations Millennium Action Plan Health InterNetwork World Health Organization April 2001.
Welcome to Department of Electrical Engg.. About Electrical Engineering Electrical engineering encompasses all devices and systems that operate electrically.
DOP - A CPU CORE FOR TEACHING BASICS OF COMPUTER ARCHITECTURE Miloš Bečvář, Alois Pluháček and Jiří Daněček Department of Computer Science and Engineering.
1 Quarterly Technical Report 1 for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department.
1 SERIAL PORT INTERFACE FOR MICROCONTROLLER EMBEDDED INTO INTEGRATED POWER METER Mr. Borisav Jovanović, Prof.dr Predrag Petković, Prof.dr. Milunka Damnjanović,
Research Project Grant (RPG) Retreat K-Series March 2012 Bioengineering Classroom.
The Scholarly Journal Archive TAIPEI 19 OCTOBER, 2005.
EECS 318 CAD Computer Aided Design LECTURE 1: Introduction.
1 Integration Verification: Re-Create or Re-Use? Nick Gatherer Trident Digital Systems.
Building An Academic Career
M. McCorquodale University of Michigan Electrical Engineering & Computer Science Mobius Integrated Systems Corporation Ann Arbor, MI January, 2001 Michael.
Presenter : Ching-Hua Huang 2013/7/15 A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation Citation : 15 Adir, A., Copty, S.
VLSI & ECAD LAB Introduction.
2 nd Annual Babcock/Eno River Capital Elevator Competition March 31, 2001 Michael McCorquodale, Chief Executive Officer Mobius Integrated Systems Corporation.
CMP 4202: VLSI System Design Lecturer: Geofrey Bakkabulindi
A centre of expertise in digital information management UKOLN is supported by: University of Bath Roadmap for EPSRC Catherine Pink Institutional.
Teaching VLSI Design Considering Future Industrial Requirements Matthias Hanke
CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.
A 16-Bit Low-Power Microcontroller with Monolithic MEMS-LC Clocking
NSF IGERT proposals Yang Zhao Department of Electrical and Computer Engineering Wayne State University.
Memory and Storage Dr. Rebhi S. Baraka
FSRM TC - DTU COREP – BME CEA EUROTRAINING Microelectronics knowhow for profit EuroTraining – Supporting University Programmes in Nanoelectronics.
Pryor-Hale Business Plan Competition April 18, 2001 Michael McCorquodale, Chief Executive Officer Keith Kraver, Chief Technical Officer Mobius Integrated.
Background: VLSI Courses at Lafayette  ECE VLSI Circuit Design  Original form: “tall thin designer”  VLSI Processing  CMOS Transistor Characteristics.
CHAPTER 8 Developing Hard Macros The topics are: Overview Hard macro design issues Hard macro design process Physical design for hard macros Block integration.
- 1 - ©2009 Jasper Design Automation ©2009 Jasper Design Automation JasperGold for Targeted ROI JasperGold solutions portfolio delivers competitive.
MANISH GUPTA. Presentation Outline Introduction Motivation Content Expected Impact Funding Schemes & Budget.
Atlantic Innovation Fund Round VIII February 5, 2008.
VLSI Design System-on-Chip Design
NSF Broadening Participation in Computing Alliances (BPC-A) Introduction to Common Core Indicators of Breadth and Depth of Participation Daryl E. Chubin,
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
Course, Curriculum, and Laboratory Improvement (CCLI) Transforming Undergraduate Education in Science, Technology, Engineering and Mathematics PROGRAM.
Fire Emissions Network Sept. 4, 2002 A white paper for the development of a NSF Digital Government Program proposal Stefan Falke Washington University.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
Computer Architecture Chapter (5): Internal Memory
Microelectronics for HEP A. Marchioro / CERN-PH-ESE.
Different Types of Integrated Circuits. Introduction: Different Types of Integrated Circuits Every electronic appliance we use.
Dividing Up the Work / production workshop / february 2009 Except where otherwise noted, this work is available under a Creative Commons Attribution 3.0.
XML Interoperability & Convergence ISO XML Working Group (WG 10) XML on Wall Street November 20th, 2001 John Goeller.
ALICE INDUSTRIAL AWARD for its collaboration to the ALTRO Chip
Intelligent Design of Electronic Assets (IDEA) Workshop
Overview of Embedded SoC Systems
William Stallings Computer Organization and Architecture 7th Edition
Quarterly Technical Report III for Pittsburgh Digital Greenhouse
CHIP DESIGNING GROUP MEMBERS :- Varunavi Neharika Daksh Anubhav
1.Introduction to Advanced Digital Design (14 marks)
Presentation transcript:

UMIPS: A Semiconductor IP Repository for IC Design Research and Education Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale and Richard B. Brown Solid State Electronics Laboratory Center for Wireless Integrated Microsystems Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA American Society of Engineering Education Annual Conference, Salt Lake City, 2004

2 Presentation Outline Overview of Semiconductor IP Recent Research Founding UMIPS UMIPS Standards and Framework UMIPS in the Classroom Conclusion Overview Research UMIPS Standards Classroom Conclusion

3 Overview of Semiconductor IP Semiconductor IP: What is it? –Essentially blueprints or code which describe IC subcircuits –Typically IP is instantiated into larger IC designs –Reduces design cycle time –Focuses design effort on in-house expertise IP use now a cornerstone of commercial IC design –Many commercial resources –Almost no resources in the research environment Could IC research and coursework benefit from IP? Are the benefits of IP use tangible? Overview Research UMIPS Standards Classroom Conclusion

4 Overview of Semiconductor IP Semiconductor design-productivity gap –Design productivity increasing by ~28%/yr. –Capacity increasing by ~58%/yr. ASIC vs. SoC –ASIC productivity increased by 2.5X from –SoC productivity increased by 7X from Why the difference? –IP design and reuse Challenges –Need for repositories and standards –Need for analog/RF and mixed-signal IP –VCX, D&R, etc. exist for industry, what about the research community? UMIPS –University of Michigan Intellectual Property Source –Developed for all IC IP: digital, analog, RF, and MEMS IP Overview Research UMIPS Standards Classroom Conclusion

5 Recent Research Overview Research UMIPS Standards Classroom Conclusion Memory CMOS-MEMS CLK Ref. Memory Peripherals Pipeline Analog Front End Analog Test Cache 16-Bit MS MCU 16-bit low-power MCU 12-bit  -ADC Integrated RF-MEMS Clock Reference Physical Design TSMC 0.18  m MM/RF ~3.5 million transistors 12.8mm 2

6 Recent Research Overview Research UMIPS Standards Classroom Conclusion External Memory Memory Management Unit FetchDecodeExecute Register Files Boot ROM 64KB RAM Timer X2 USART X3 SPI X2 Test Int. ADC Int. Loop Cache CMOS-MEMS Clock Reference PGA Buffer V in+ V - Analog Front End  ADC

7 Founding UMIPS UMIPS Founding –Logical outgrowth of large scale VLSI projects at Michigan Previously described IP marked the founding contributions UMIPS Mission –UMIPS is a collaborative effort between Electrical Engineering and Computer Science students, faculty, and researchers to leverage each others’ integrated circuit development in the pursuit of cutting-edge microsystems and SoC research Motivation: Benefits of design reuse to research –Elimination of repetitive basic design activities –Focus IC design effort on novel research –Research IP repository can support many semiconductor technologies –Student experience with IP development –Potential for collaboration with IC design courses Overview Research UMIPS Standards Classroom Conclusion

8 Founding UMIPS: The Main Internet Portal Overview Research UMIPS Standards Classroom Conclusion

9 UMIPS Standards and Framework: Overview UMIPS is managed by founders at UMICH –Accessible by all researchers in the academic community –For noncommercial use only UMIPS submissions –Received and posted submissions from UMICH & other institutions Access –Main internet portal: –Nonproprietary descriptions of the IP components UMIPS IP Checkout –Submit a request for IP to the management team –Authentication information provided for the specific IP Overview Research UMIPS Standards Classroom Conclusion

10 UMIPS Standards and Framework: Supported IP UMIPS supported IP –Application formats: functional and structural –Delivery formats: hard, soft, and design methodology formats –Deliverables for each format described in references Organized by function and by process technology –All MOSIS supported processes –Future: UMIPS will support IP specific internal solid-state electronics laboratory as well as MEMS foundries Overview Research UMIPS Standards Classroom Conclusion

11 UMIPS Standards and Framework: Quality Control Pre-silicon verified –Simulation, extraction, and verification –Least rigorous Post-silicon verified –Verified by test –Most rigorous Uninstantiated –Has not been developed into larger project Instantiated –Has been developed into larger project –Indicates deliverables are indeed sufficient Overview Research UMIPS Standards Classroom Conclusion

12 UMIPS Standards and Framework: Challenges General Management Qualification and auditing –Most rigorous and time-consuming, but the most important –Automation of portions of these activities expected in the future Participation difficult to stimulate –Breadth of requirements for depositing IP into UMIPS –Award program: most highly utilized IP and the most novel IP submissions –Organic growth Technical challenges –Managing IP deliverables across various tool suites –Analog and digital design suites differ –Incompatible verification decks Overview Research UMIPS Standards Classroom Conclusion

13 UMIPS in the Classroom UMIPS presents unique classroom opportunity –Students design critical functional blocks as part of coursework –These blocks can be checked into UMIPS –Student researchers can check out blocks and fab them into designs Highlights –Students in the classroom can see their designs turn into Si and potentially gain authorship of published research –Researchers can focus design effort on their block –Researchers can solicit design projects from courses –Potential for collaboration between IC researchers and educators Targeted Courses –i.e. Monolithic Amplifier Circuits: Basic Op-Amp Project Overview Research UMIPS Standards Classroom Conclusion

14 Conclusion Clear benefits to IP use in IC development cycles Industry has developed many resources for IP use but research resources are immature UMIPS founded logically out of large VLSI design efforts at Michigan and extended to much broader scope UMIPS has received submissions from several universities and countries UMIPS IP has been utilized in several IC design cycles since its founding UMIPS aims to expand into the classroom both at Michigan and other interested Universities next year Overview Research UMIPS Standards Classroom Conclusion