Design Exploration for Wireless Embedded Systems: the Voic Pager Example Fernando De Bernardinis EE249 Project - Fall 1998

Wireless Embedded Systems Complex designs: Architecture/Functionality/Protocol Hardware/Software/Analog Complex simulation –Analog effects –Simulation times –Analog/Digital interactions (corrections) Protocols map digital functionalities to analog front-ends –Computation load vs. Analog complexity –Flexibility vs. Power and Cost

Starting point Design example carried out at UCB and Cadence (a Voic pager) However, not a good high level description for the Felix methodology: –originally carried out in BoNES –few design choices, blackboxes include BoNES files and therefore “hide” functionalities Two primary objectives: –Re-implement the protocol layer –Include some detail of the modulation scheme

The Voic Pager One-way voice pager system 1 cell only, ~1km radius, industrial site env. BW requirements: 250Kbps ISM band MHz FCC requirements –> 50 hop channels, –< 1W max power –< 500 kHz BW/channel (20 dB) –< 0.4 sec hop time System - level solution so far: –Slow FH system, 50 channels, 50ms hop time –Each hop ch.: 8 ch. FDMA, each ch. 8 TDMA slots

Protocol Layer Converts bits to frames, i.e. raw bits to control and message data Analog requirements introduce guard and spacers sections –synchronize receiver at the beginning of frame –separate different messages (TDMA) Relevant trade-off point: –short frames overhead (control vs. load) –long frames large miss penalty Therefore: parameterized protocol for optimization purposes

Protocol Layer Several parameters to determine Guard and Spacers depend on the analog front-end and on the modulation used Guard Header ControlSpacers Messages SuperFrameFrameProtocolReserved Control 0 Control 1 Control 2 Control 3 AddressSF ReferSlot Type Hop offsetLengthReserved MSG0MSG1MSG2MSG3

Protocol Specification Protocol  Regular Expression  CFSM Hierarchical CFSM

Implementation Problems Hierarchy –Felix does not support hierarchical STDs Loop issues –Self-loop actions imply the increment of an index i and the acquisition of one or more elements h[i] m[i] –There is no way of specifying order in the actions in current implementation of STDs Therefore, WhiteC models –dynamic delay estimation –less intuitive debugging

Physical Layer QPSK modulation 1 Mb/s data rate Bit level simulation: –Slow simulation time/Accuracy –Separation of testbench from behavior –Better models through SPW (import Dataflow MoC)

Testbench generator Overall Behavior Model Voic model

Architecture Models 10 MHz 16 bit MCU Pre-emptive static priority RTOS 16 bit/5 MHz bus FIFO arbitrated Interrupt bus to model the interaction between the ASIC and th MCU ASIC to implement the physical layer

Other Architectures Other possibilities: 50 MHz 32 bit MCU –32 bit modeled through the fuzzy instruction set 32 bit/25 MHz bus Many blocks in the systems are “blackboxes”, which are provided with a static delay independent of the MCU This comes from previous BoNES C++ models, and it is quite difficult to extrapolate new delays without having a deep knowledge of each block implementation 3216

Mapping - 1 The physical layer is mapped on the ASIC The protocol model is mapped on software All remaining blocks are mapped on software The ASIC/MCU communication is mapped on the Interrupt Bus Other communications are mapped on the Data Bus

Mapping - 2 Simulation show that the protocol layer cannot be mapped on the MCU –The block is activated at 250kS/s input rate, therefore is not manageable via interrupts –RTOS context switch overhead is 2  s Therefore, the protocol layer is mapped on hardware –estimated delay 0.8  s The interrupt bus exploit a different communication

Results

Conclusions A parameterized protocol has been created for the voic pager and described as a WhiteC block A basic modulator has been inserted in the physical layer An architecture has been selected and some mappings were run –Protocol cannot be mapped on software No further mapping are possible with the “blackbox” description of the system Some limitations of the current implementation of STDs were pointed out