Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Scan design techniques J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias Porto - PORTUGAL Tel / Fax: /

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)2 Objectives To introduce the basic concepts in design for test To prepare the introduction of the standard boundary-scan test architecture

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)3 Outline Testability and test generation in sequential circuits Testability improvement via ad hoc solutions Structured approaches to design for testability

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)4 Test generation for sequential circuits Direct application of the D-algorithm leads to the combinational circuit inputs and outputs, not necessarily to primary inputs or outputs

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)5 Test generation - step 1

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)6 Test generation - step 2

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)7 Test generation - step 3 The second clock cycle is applied with A=1 and guarantees fault detection, because the circuit is now brought to a state where fault activation and fault propagation are simultaneously possible. F CLK A fault-free X

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)8 The general case is however much more complex... The D-algorithm does not necessarily lead to circuit primary inputs and outputs Knowledge of the state transition diagram is required It may happen that the fault affects the state transition diagram, in which case the required sequence at the circuit primary inputs becomes even harder to find

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)9 The case of Y Test vector generation for a fault that affects the state transition diagram will help us to understand the problem

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)10 The case of Y (cont.) Q1,Q0= Modification in the state transition diagram: 0, Q1,Q0=00 States 1 and 3 (Q0=1) are no longer accessible Q1 Q0

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)11 Ad hoc testability improvements Design rules or amendments to avoid or minimise test vector generation problems Major drawbacks: –Not always reusable –Testability depends largely on the type of circuit

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)12 Some ad hoc testability rules Split counters to avoid high numbers of clock cycles until the required output combination is achieved Include reset and preset lines (synchronous or asynchronous) Partition large circuits and add extra inputs and outputs for direct controllability and observability of internal nodes

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)13 Structured Design for Testability (DfT) Structured DfT methodologies enable a simple way to drive the circuit to any given state in a fixed (and short) number of clock cycles Does structured DfT have drawbacks? –Design rules (design styles) have to accepted –Additional silicon area, more pins and higher propagation delays… but is this an additional cost?

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)14 The scan design principle The scan design principle consists of inserting a 2:1 multiplexer between the input of every D flip-flop and its driving logic

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)15 Scan design advantages (1) Problem: Part of the combinational circuit inputs are not directly controllable, since they come from the D-FF outputs (these nodes define the present state of the circuit) Solution: Scan flip-flops enable direct controllability of the D-FF outputs through a simple procedure with a fixed number of clock cycles

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)16 Better controllability through scan design (1) Example Take the circuit to state 110, starting from state 100 (intrusive)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)17 Better controllability through scan design (2)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)18 Better controllability through scan design (3)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)19 Better controllability through scan design (4)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)20 Better controllability through scan design (5)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)21 Scan design advantages (2) Problem: Part of the combinational circuit outputs are not directly observable, since they go to the D-FF inputs (these nodes define the circuit next state) Solution: Scan flip-flops enable direct observability of the D-FF inputs through a simple procedure with a fixed number of clock cycles

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)22 Better observability through scan design (1) Example Observe the next state (eventually non-intrusive)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)23 Better observability through scan design (2)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)24 Better observability through scan design (3)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)25 Better observability through scan design (4)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)26 Better observability through scan design (5)

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)27 DfT: Eventually an overhead The 2:1 muxs increase the propagation delay and require additional silicon area and pins, but will this increase cost? How do we quantify the benefits of easier test vector generation and application? Design freedom was traded for higher testability, but partial scan design might be a preferred intermediate solution