Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 1

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 2 Main program code Interrupt code Interrupt Interrupt return

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 3  ARM runs in 1 of 6 modes  each mode has (some) unique registers  mode is available to outside world (fi: for a memory managment unit – not in LPC2106)  current mode is in the CPSR register  2 ‘normal’ interrupts: IRQ, FIQ

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 4 ARM User Programming model r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) CPSR 31 0 N Z C V r13: stack pointer r14: link register 31 0 Status register mode

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 5 All ARM registers 

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 6  switch to the interrupt mode (IRQ or FIQ) (this switches to the new set of registers!)  copy PC to LR  copy CPSR to SPSR  set PC to start of interrupt code (fixed) notes:  Almost the same as a procedure call (BL)  no use of the stack  No (automatic) saving of registers

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 7  ‘normal’ interrupts  Private LR (of course)  Private SP  no other private registers (must save users registers)

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 8  typically used for ‘simple & fast’ processing  Private LR (of course)  Private SP  Private R6.. R12  Low latency:  no need to save user’s registers  no need to initialise FIQ registers!

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 9  Vectored Interrupt Controller  between interrupt sources and the ARM core  handles: priorities and vectoring

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 10 1.FIQs 2.Vectored IRQs 3.Non-vectored IRQs While the code for an interrupt is running lower interrupts are blocked  The interrupt code must inform the VIC when its done!

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 11 Each  FIQ  vectored IRQ has a unique vector. In most cases this will be the start address of the code that handles the interrupt. All non-vectored IRQs share one vector, the interrupt code must inquire which interrupt has occured.

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 12  32 sources possible  16 hardware sources implemented on an LPC 2106

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Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 22  16 vector slots  0 has highest priority, 15 lowest  each slot contains  enable bit  the interrupt source (0..31)  the vector address (32 bits)

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 23 I

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Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 26 This is not mentioned in the Philips manuals 

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 27  probably: reserve and set the interrupt stack  make sure the hardware vector points to your code  configure the peripheral to generate interrupts  enable the interrupt source  select FIQ or IRQ  (vectored) set source, enable, vector  (non-vectored IRQ) set default vector  enable interrupts

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 28 ldrr2, = … mrsr0, Original PSR value bicr0, r0, Clear the mode bits orrr0, r0, Set IRQ mode bits msrcpsr_c, Change the mode movsp, r2 bicr0, r0, Clear the mode bits orrr0, r0, Set Supervisor bits msrcpsr_c, Change the mode

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 29 ldrpc, reset vector ldrpc, undefined instruction ldrpc, software interrupt ldrpc, prefetch abort ldrpc, data abort ldrpc, reserved ldrpc, [pc, IRQ. load from VICVectAddr ldrpc, FIQ

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 30  (probably) save registers  do what you have to do  clear the interrupt source  write to VicVectAddr  return: subspc, lr, #4

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 31 Why?  protect data that is used by both main and interrupts  protect code that must execute with a fixed timing

Computertechniek Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology 32 __disable_interrupts: mrsr0, CPSR orrr0, r0, disable IRQ interrupts msrCPSR_fsxc, r0 movpc, lr __enable_interrupts: mrsr0, CPSR bicr0, r0, enable IRQ interrupts msrCPSR_fsxc, r0 movpc, lr