Stonewalled Progress of Computing Efficiency 1 Reiner Hartenstein (keynote) SA - Sep 1 16:10 - 16:50

Slides:



Advertisements
Similar presentations
Microprocessors Typical microprocessor controlled devices: Camera, mobile phone, stereo, mp3 player, electronic toys… High-level microprocessor controlled.
Advertisements

ISA Issues; Performance Considerations. Testing / System Verilog: ECE385.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /15/2013 Lecture 11: MIPS-Conditional Instructions Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER.
MIPS Assembly Language CPSC 321 Computer Architecture Andreas Klappenecker.
The University of Adelaide, School of Computer Science
The von Neumann Syndrome Reiner Hartenstein TU Kaiserslautern TU Delft, Sept 28, (v.2)
Chapter 2 - Problem Solving
Reconfigurable Computing and the von Neumann Syndrome Reiner Hartenstein.
TESTING LOOPS ● Simple Loops ● Nested Loops ● Concatenated Loops ● Unstructured Loops.
Chapter 8 . Sequence Control
Team 2 Week 6 Presentation The Attack of the Slow Moving Computers! AlexDaveKevinMike.
Basic Building Blocks of Programming. Variables and Assignment Think of a variable as an empty container Assignment symbol (=) means putting a value into.
An Object-Oriented Approach to Programming Logic and Design Chapter 7 Arrays.
CSCI/CMPE 4341 Topic: Programming in Python Chapter 3: Control Structures (Part 1) – Exercises 1 Xiang Lian The University of Texas – Pan American Edinburg,
How to cope with the Power Wall Reiner Hartenstein TU Kaiserslautern DRAFT PATMOS 2015, the 25 th International Workshop on Power and Timing Modeling,
How to cope with the Power Wall Reiner Hartenstein TU Kaiserslautern PATMOS 2015, the 25 th International Workshop on Power and Timing Modeling, Optimization.
How to cope with the Power Wall Reiner Hartenstein TU Kaiserslautern IEEE fellow FPL fellow SDPS fellow PATMOS 2015, the 25 th International.
Cosc 2150: Computer Organization
9.2 Pipelining Suppose we want to perform the combined multiply and add operations with a stream of numbers: A i * B i + C i for i =1,2,3,…,7.
DSD2001 Reconfigurable Computing: the Roadmap to a New Business Model – and its Impact on SoC Design TS4: Tuesday, hrs Reiner Hartenstein University.
CPS120 Introduction to Computer Science Iteration (Looping)
CPS120 Introduction to Computer Programming The Programming Process.
CPS120: Introduction to Computer Science Decision Making in Programs.
ITEC 352 Lecture 14 ISA(6). Review Questions? Beginning / End Memory locations Variable / Memory syntax PSR Loops / Branches.
Bottlenecks of SIMD Haibin Wang Wei tong. Paper Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements One IEEE.
VLSI-SoC 2001 IFIP - LIRMM Stream-based Arrays: Converging Design Flows for both, Reiner Hartenstein University of Kaiserslautern December 2- 4, 2001,
Control Structures CPS120: Introduction to Computer Science Lecture 5.
Chapter 4 The Processor. Chapter 4 — The Processor — 2 Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined.
COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE LECTURE # 4 BY MUHAMMAD JAFER 1.
M. Mateen Yaqoob The University of Lahore Spring 2014.
Computer Architecture and Operating Systems CS 3230 :Assembly Section Lecture 5 Department of Computer Science and Software Engineering University of Wisconsin-Platteville.
Reduced Instruction Set Computers. Major Advances in Computers(1) The family concept —IBM System/ —DEC PDP-8 —Separates architecture from implementation.
Computer Architecture CSE 3322 Lecture 3 Assignment: 2.4.1, 2.4.4, 2.6.1, , Due 2/3/09 Read 2.8.
Reconfigurable HPC Notes on datastream-based FFT
CPS120 Introduction to Computer Science Iteration (Looping)
More on Pipelining 1 CSE 2312 Computer Organization and Assembly Language Programming Vassilis Athitsos University of Texas at Arlington.
PHY 201 (Blum)1 Stacks Based in part on material from Chapters 4 & 5 in Computer Architecture by Nicholas Carter.
The LC-3 – Chapter 5 COMP 2620 Dr. James Money COMP
Flowcharts C++ Lab. Algorithm An informal definition of an algorithm is: a step-by-step method for solving a problem or doing a task. Input data A step-by-step.
Polya’s 4-step Process 1.Understand the problem 2.Devise a plan 3.Carry out the plan 4.Look back, review results.
Engineering Computing I Chapter 3 Control Flow. Chapter 3 - Control Flow The control-flow of a language specify the order in which computations are performed.
Flow Control in Imperative Languages. Activity 1 What does the word: ‘Imperative’ mean? 5mins …having CONTROL and ORDER!
1 3 Computing System Fundamentals 3.2 Computer Architecture.
Programming Techniques
G043: Lecture 12 Basics of Software Development Mr C Johnston ICT Teacher
Reiner Hartenstein University of Kaiserslautern
Topics to be covered Instruction Execution Characteristics
Achieving Turing Completeness
Reiner Hartenstein University of Kaiserslautern
Computer Architecture & Operations I
Topics discussed in this section:
Memory Organisation for Datastream-based Reconfigurable Computing
The fetch-execute cycle
Team A.W.E.S.O.M.-O 4000 February 27, 2007.
CPS120: Introduction to Computer Science
Repetition and Loops while do while for continue break
المدخل إلى تكنولوجيا التعليم في ضوء الاتجاهات الحديثة
Higher Computing Using Loops.
Embedded Architectures: Configurable, Re-configurable, or what?
CS-401 Computer Architecture & Assembly Language Programming
Early - I can develop a sequence of instructions and run them using programmable devices or equivalent Designs a simple sequence of instructions/algorithm.
How to cope with the Power Wall
The structure of programming
Introduction to Computer Science
Print the following triangle, using nested loops
The structure of programming
Thinking procedurally
Review: What is an activation record?
Iteration Learning Objective: to be able to design algorithms that use iteration.
Stage 21: Artist: Patterns
Presentation transcript:

Stonewalled Progress of Computing Efficiency 1 Reiner Hartenstein (keynote) SA - Sep 1 16: :50

© 2012, TU Kaiserslautern 2 x y *> Declarations HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag; goto PixMap[1,1] HalfZigZag; SouthWestScan uturn (HalfZigZag) HalfZigZag data counter HalfZigZag EastScan is step by [1,0] end EastScan; SouthWestScan is loop 8 times until [1,*] step by [-1,1] endloop end SouthWestScan; SouthScan is step by [0,1] endSouthScan; NorthEastScan is loop 8 times until [*,1] step by [1,-1] endloop end NorthEastScan; Flowware language example ( MoPL ) JPEG zigzag scan pattern 37

© 2012, TU Kaiserslautern Duality of procedural Languages Flowware Languages read next data item goto (data address) jump to (data address) data loop data loop nesting data loop escape data stream branching yes: internally parallel loops 3 Software Languages read next instruction goto (instruction address) jump to (instruction address) instruction loop instruction loop nesting instruction loop escape instruction stream branching no: internally parallel loops Asymmetry But there is an Asymmetry program counter: data counter(s): more simple: no ALU tasks no tunnel view!