Circuiti sequenziali1 Progettazione di circuiti e sistemi VLSI Anno Accademico Lezione Circuiti sequenziali

2 Sequential Logic 2 storage mechanisms positive feedback charge-based

Circuiti sequenziali3 Naming Conventions In our text: – a latch is level sensitive – a register is edge-triggered There are many different naming conventions –For instance, many books call edge- triggered elements flip-flops –This leads to confusion however

Circuiti sequenziali4 Latch versus Register  Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ

Circuiti sequenziali5 Latches

Circuiti sequenziali6 Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

Circuiti sequenziali7 Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

Circuiti sequenziali8 Maximum Clock Frequency Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay t clk-Q + t p,comb + t setup = T

Circuiti sequenziali9 Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

Circuiti sequenziali10 Meta-Stability Gain should be larger than 1 in the transition region Meta-Stability Gain should be larger than 1 in the transition region

Circuiti sequenziali11 Meta-Stability Gain should be larger than 1 in the transition region

Circuiti sequenziali12 Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

Circuiti sequenziali13 Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

Circuiti sequenziali14 Mux-Based Latch

Circuiti sequenziali15 Mux-Based Latch NMOS onlyNon-overlapping clocks

Circuiti sequenziali16 Master-Slave (Edge- Triggered) Register Two opposite latches trigger on edge – Master negative latch/ Slave positive latch Also called master-slave latch pair

Circuiti sequenziali17 Master-Slave Register Multiplexer-based latch pair Positive edge triggered

Circuiti sequenziali18 Reduced Clock Load Master-Slave Register

Circuiti sequenziali19 Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

Circuiti sequenziali20 Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset

Circuiti sequenziali21 Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building memory cell

Circuiti sequenziali22 Storage Mechanisms D CLK Q Dynamic (charge-based) Static

Circuiti sequenziali23 Making a Dynamic Latch Pseudo- Static

Circuiti sequenziali24 Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static

Circuiti sequenziali25

Circuiti sequenziali26 Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

Circuiti sequenziali27 CLK 1/1 0/0

Circuiti sequenziali28 Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)

Circuiti sequenziali29

Circuiti sequenziali30 Including Logic in TSPC AND latch Example: logic inside the latch

Circuiti sequenziali31 TSPC Register

Circuiti sequenziali32 Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell:

Circuiti sequenziali33 Pulsed Latches

Circuiti sequenziali34 Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :