doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 1 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [IEEE b High Rate Alt-PHY proposals - Further Performance Comparison] Date Submitted: [10 Nov, 2004] Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore] Address: [21 Heng Mui Keng Terrace, Singapore ] Voice: [ ] FAX: [ ] Re: [Response to the call for proposal of IEEE b, Doc Number: b] Abstract:[This presentation compares all proposals for the IEEE b PHY standard.] Purpose:[Proposal to IEEE b Task Group] Notice:This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release:The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 2 Background –Main contribution of current doc is to provide further simulation results based on 1000 channel realisation, for the PHY proposals using coherent detection –Previous comparison used 100 channel realisation, as in IEEE Doc b –Performance comparison herein done with {0,1,2} cyclic chip extension {1,2,3} RAKE fingers

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 3 Updates –Corrected 3-RAKE multipath performance for all proposals (due to programme bug in previous version) –Included PSSS performance with Precoding –Determined RMS Delay Spread threshold below which cyclic chip extension is not necessary –Include 868 MHz multipath performance with raised cosine filter (roll-off factor = 0.2) –Stated Recommendation based on realistic channel RMS delay spread –915MHz Transmit PSD for COBI-16

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 4 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code SetE 16 G 16 C8C8 F 31 Candidate for915MHz 868MHz DescriptionOrthogonal 16-DSSS 16-chip for Coh. Chip Despreading 8-chip for Coh. Chip Despreading PSSS ProposerHelicommI2RI2RI2RI2RDr. Wolf & Assoc. Doc # Sym-Chip mapping OrthogonalCyclic & Odd Bit Inversion Multi-code Bit/sym44415 Chip/Sym cyclic extension Bit/chip ~0.47 Root Sequence N.A.2F535C08B3E375 Source: b

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 5 System Parameters for low GHz Bands Ch #0 868MHz band Ch # – 924 MHz Band Bandwidth600 kHz2 MHz Code Set Candidate 8-chip COBI C 8 PSSS F 31 8-chip COBI C 8 PSSS F 31 8-chip COBI C 8 PSSS F chip COBI G 16 DSSS E 16 Chip rate300kcps400kcps500kcps1Mcps Pulse shape Raised cosine (roll off = 1) Raised cosine (roll off = 0.5) Raised cosine (roll off = 0.2) Half- sine ModulationBPSK /ASK BPSK /ASK BPSK /ASK OQPS K Data rate150 kbps kbps 200 kbps kbps 250 kbps kbps 250 kbps

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 6 Comparison Methodology –Multipath robustness performance Investigation done with –Zero, one and two Cyclic chip(s) extension –One, two & three RAKE fingers –Bandwidth efficiency (bps / Hz) –RF requirement –Memory requirement

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 7 Multipath Realisations 1000 Channel Realisations at each RMS Delay Spread

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 8 Multipath Realisations 1000 Channel Realisations at each RMS Delay Spread

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 9 The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values) Proposed Symbol-to-Chip Mapping (8-chip Code Set C 8 ) Decimal ValueBinary SymbolChip Value (Root – 5C)

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 10 Other Root Sequences (8-chip C 8 for Coherent Despreading only) The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 11 DSSS Sequence E 16 Decimal Symbol Binary SymbolChip Values Source doc.: IEEE b

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 12 PSSS Sequence F 31 (15 bit/32 chip) Source doc.: IEEE b

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 13 Proposed Symbol-to-Chip Mapping (16-chip Code Set G 16 ) The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values) Decimal ValueBinary SymbolChip Value (Root - 2F53)

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 14 Other Root Sequences (8-chip G 16 for Coherent Despreading only) The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 15 Multipath Performance (COBI 1Mcps using O-QPSK For 16-chip COBI Sequence, No cyclic chip is needed when 3 RAKE is used.

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 16 Multipath Performance (COBI 8-chip) For 8-chip COBI Sequence, 1 Chip Extension is needed even with 3-RAKE, due to weaker despreading strength (shorter code length).

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 17 Multipath Performance (DSSS) For DSSS, No cyclic chip is needed when 3 RAKE is used.

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 18 Multipath Performance (PSSS) For PSSS, best performance with 2 RAKE fingers + 1 chip extension. Precoding (according to b) & 3 rd RAKE do not seem to help.

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 19 What happened to PSSS? While other schemes enjoy better multipath performance with more RAKE fingers, PSSS can only use up to 2 fingers as the 3 rd RAKE is dominated by adjacent parallel bit sequence. PSSS is inter-parallel sequence interference limited Neighbouring parallel sequence is using M-Seq with 2 cyclic shifts in PSSS parallel sequence construction Source doc.: IEEE b

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide MHz Coherent Receiver Performance Under Various Channel Delay Spread Even upto 1.33us RMS Delay Spread 1 chip extension is NOT necessary for 16-chip sequence (COBI-16 & DSSS) if sufficient RAKE fingers (at least 3) are used, even in dense multipath environment General performance comparison: COBI sequence (16 chip) > DSSS Sequence (16 chip)

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide MHz Coherent Receiver Performance Under Various Channel Delay Spread Raised cosine filter (roll-off factor = 1.0) Gives 300 kcps Even upto 1.33us RMS Delay Spread 1 chip extension is NOT necessary for COBI-8 if sufficient RAKE fingers (at least 3) are used, even in dense multipath environment General performance comparison: COBI sequence (8 chip) > PSSS Sequence

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide MHz Coherent Receiver Performance Under Various Channel Delay Spread Raised cosine filter (roll-off factor = 0.2) Gives 500 kcps Even upto 1.33us RMS Delay Spread 1 chip extension is NOT necessary for COBI-8 if sufficient RAKE fingers (at least 4) are used, even in dense multipath environment General performance comparison: COBI sequence (8 chip) > PSSS Sequence

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 23 Summary of Comparsion Code SetE 16 G 16 C8C8 F 31 Candidate for915MHz 868MHz DescriptionOrthogonal 16- DSSS 16-chip for Coh. Chip Despreading 8-chip for Coh. Chip Despreading PSSS ProposerHelicomm I2RI2R I2RI2RDr. Wolf & Assoc. Doc # Sym-Chip mapping Orthogonal Cyclic & Odd Bit Inversion Multi-code Bit/sym Chip/Sym cyclic extension Bit/chip /32 ~0.47 Multipath performance GoodBestBetterGood Memory requirement High 16 sequence Low Single sequence Low Single sequence Low Single sequence RF linearity requirement Low Moderate ~ high Note : Red - desirable

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 24 Can Non-Coherent Detection be used for COBI-16? The COBI are designed to give best performance with coherent detection receiver. Can receiver employs Differential Chip detection?: Yes, COBI sequence (16 chip) can handle multipath channels with RMS delay spread upto 0.15us for 915MHz bands using 1Mcps, which normally corresponds to short range indoor environment

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 25 The COBI are designed to give best performance with coherent detection receiver. Can receiver employs Differential Chip detection?: Yes, COBI sequence (8 chip) can handle multipath channels with RMS delay spread upto 0.1us for 868MHz band using both 300kcps (roll-off factor = 1,0) and 500kcps (roll-off factor = 0.2), at even shorter range Can Non-Coherent Detection be used for COBI-8?

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 26 To combat inter-chip interference due to realistic channel delay spread with RMS delay spread upto 1.33us (e.g. industry application space): COBI 16-chip is recommended for 915MHz bands; COBI 8-chip is recommended for 868MHz bands. RAKE combining (with at least 3 fingers) is necessary in receiver to combine path diversity; (this does not affect standard) Chip extension is NOT necessary to avoid inter-symbol interference, if sufficient RAKE fingers are employed Differential chip despreading can also be used in shorter transmission range environment,e.g. residential space, where multipath channel RMS delay spread is upto 0.15us Multipath Performance Summary (Coherent Chip Despreading)

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 27 System Parameters for low GHz Bands Ch #0 868MHz band Ch # – 924 MHz Band Bandwidth600 kHz2 MHz Code Set Candidate 8-chip COBI C 8 PSSS F 31 8-chip COBI C 8 PSSS F 31 8-chip COBI C 8 PSSS F chip COBI G 16 DSSS E 16 Chip rate300kcps400kcps500kcps1Mcps Pulse shape Raised cosine (roll off = 1) Raised cosine (roll off = 0.5) Raised cosine (roll off = 0.2) Half- sine ModulationBPSK /ASK BPSK /ASK BPSK /ASK OQPS K Data rate150 kbps kbps 200 kbps kbps 250 kbps kbps 250 kbps

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 28 Beyond fc +/- 1.2 MHz, the highest sidelobe level is ~39 dB below the total transmit power and ~30 dB below the highest point in the PSD Therefore, ~10 dB of margin to the -20 dBr spec. For a device transmitting +10 dBm, there is ~9 dB of margin to the -20 dBm absolute spec. Propose to be same as existing 915MHz Mask 915 MHz Band Transmit PSD (COBI-16)

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 29 Supporting Materials

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 30 What leads to Multipath robustness? Frequency selectivity leads to Inter-chip interference, and that is the killer…. To overcome, code must have good autocorrelation properties, i.e. low sidelodes Coherent Receiver Multipath Performance

doc.: IEEE b Submission Nov 2004 Francois Chin, Institute for Infocomm Research (I 2 R) Slide 31 COBI, maintain constant module, can at best achieve zero auto- correlation within 2 chips from cor. Peak; that is good enough to handle ICI of upto 2 chip periods DSSS, comprising Walsh sequences, is not designed with auto-correlation sidelodes in mind PSSS, uses flexibility in amplitude to achieve low (zero?) auto- correlation throughout for each parallel sequence. However, it is inter-parallel sequence interference limited How these codes achieve Multipath robustness? COBI 8-chip autocorrelation matrix COBI 16-chip autocorrelation matrix