Area-Effective FIR Filter Design for Multiplier-less Implementation Tay-Jyi Lin, Tsung-Hsun Yang, and Chein-Wei Jen Department of Electronics Engineering.

Slides:



Advertisements
Similar presentations
FINITE WORD LENGTH EFFECTS
Advertisements

Cost-Effective Pipeline FFT/IFFT VLSI Architecture for DVB-H System Present by: Yuan-Chu Yu Chin-Teng Lin and Yuan-Chu Yu Department of Electrical and.
A Practical Guide to Troubleshooting LMS Filter Adaptation Prepared by Charles H. Sobey, Chief Scientist ChannelScience.com June 30, 2000.
New Attacks on Sari Image Authentication System Proceeding of SPIE 2004 Jinhai Wu 1, Bin B. Zhu 2, Shipeng Li, Fuzong Lin 1 State key Lab of Intelligent.
Efficient Bit Allocation and CTU level Rate Control for HEVC Picture Coding Symposium, 2013, IEEE Junjun Si, Siwei Ma, Wen Gao Insitute of Digital Media,
1 Outline  Introduction to JEPG2000  Why another image compression technique  Features  Discrete Wavelet Transform  Wavelet transform  Wavelet implementation.
{ Fast Disparity Estimation Using Spatio- temporal Correlation of Disparity Field for Multiview Video Coding Wei Zhu, Xiang Tian, Fan Zhou and Yaowu Chen.
CABAC Based Bit Estimation for Fast H.264 RD Optimization Decision
Deterministic Wavelet Thresholding for Maximum-Error Metrics Minos Garofalakis Bell Laboratories Lucent Technologies 600 Mountain Avenue Murray Hill, NJ.
Application of Generalized Representations for Image Compression Application of Generalized Representations for Image Compression using Vector Quantization.
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis 15 th IEEE International Conference on Application Specific Architectures.
Speech Enhancement Based on a Combination of Spectral Subtraction and MMSE Log-STSA Estimator in Wavelet Domain LATSI laboratory, Department of Electronic,
A DSP-Based Ramp Test for On-Chip High-Resolution ADC Wei Jiang and Vishwani D. Agrawal Auburn university.
1 Implementation of VLD and Constant Division on PAC DSP Platform Student: Chung-Yen Tsai Advisor: Prof. David W. Lin Date:
1 Channel Estimation for IEEE a OFDM Downlink Transmission Student: 王依翎 Advisor: Dr. David W. Lin Advisor: Dr. David W. Lin 2006/02/23.
1 A Unified Rate-Distortion Analysis Framework for Transform Coding Student : Ho-Chang Wu Student : Ho-Chang Wu Advisor : Prof. David W. Lin Advisor :
IC-SOC STEAC: An SOC Test Integration Platform Cheng-Wen Wu.
Built-in Adaptive Test and Calibration of DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL
Carnegie Mellon Adaptive Mapping of Linear DSP Algorithms to Fixed-Point Arithmetic Lawrence J. Chang Inpyo Hong Yevgen Voronenko Markus Püschel Department.
Motion Estimation Using Low- Band-Shift Method for Wavelet- Based Moving Picture Hyun-Wook Park, Senior Member, IEEE, and Hyung-Sun Kim IEEE Transactions.
A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation Viet L. Do and Kenneth Y. Yun IEEE Transactions on Circuits and Systems.
Sparsity-Aware Adaptive Algorithms Based on Alternating Optimization and Shrinkage Rodrigo C. de Lamare* + and Raimundo Sampaio-Neto * + Communications.
Prepared by: Hind J. Zourob Heba M. Matter Supervisor: Dr. Hatem El-Aydi Faculty Of Engineering Communications & Control Engineering.
Hossein Sameti Department of Computer Engineering Sharif University of Technology.
Digital to Analogue Conversion Natural signals tend to be analogue Need to convert to digital.
An Energy-Efficient Reconfigurable Multiprocessor IC for DSP Applications Multiple programmable VLIW processors arranged in a ring topology –Balances its.
Robust Low Power VLSI Selecting the Right Conference for the BSN FIR Filter Paper Alicia Klinefelter November 13, 2011.
Normalization of the Speech Modulation Spectra for Robust Speech Recognition Xiong Xiao, Eng Siong Chng, and Haizhou Li Wen-Yi Chu Department of Computer.
Kai-Chao Yang Hierarchical Prediction Structures in H.264/AVC.
MAXIMIZING SPECTRUM UTILIZATION OF COGNITIVE RADIO NETWORKS USING CHANNEL ALLOCATION AND POWER CONTROL Anh Tuan Hoang and Ying-Chang Liang Vehicular Technology.
Introduction to Adaptive Digital Filters Algorithms
1 Miodrag Bolic ARCHITECTURES FOR EFFICIENT IMPLEMENTATION OF PARTICLE FILTERS Department of Electrical and Computer Engineering Stony Brook University.
Graduate Category: Engineering and Technology Degree Level: Ph.D. Abstract ID# 122 On-Chip Spectral Analysis for Built-In Testing and Digital Calibration.
Frame by Frame Bit Allocation for Motion-Compensated Video Michael Ringenburg May 9, 2003.
Scheme for Improved Residual Echo Cancellation in Packetized Audio Transmission Jivesh Govil Digital Signal Processing Laboratory Department of Electronics.
A New Algorithm for Improving the Remote Sensing Data Transmission over the LEO Satellite Channels Ali Payandeh and Mohammad Reza Aref Applied Science.
Function Computation over Heterogeneous Wireless Sensor Networks Xuanyu Cao, Xinbing Wang, Songwu Lu Department of Electronic Engineering Shanghai Jiao.
VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교
Low-Power H.264 Video Compression Architecture for Mobile Communication Student: Tai-Jung Huang Advisor: Jar-Ferr Yang Teacher: Jenn-Jier Lien.
RICE UNIVERSITY “Joint” architecture & algorithm designs for baseband signal processing Sridhar Rajagopal and Joseph R. Cavallaro Rice Center for Multimedia.
Estimation of Number of PARAFAC Components
Performance Analysis of OFDM Systems with Adaptive Sub Carrier Bandwidth Suvra S. Das, Student Member, IEEE, Elisabeth De Carvalho, Member, IEEE, and Ramjee.
Area: VLSI Signal Processing.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-Graduate Project Case Study: Single-path Delay Feedback FFT Speaker: Yu-Min.
Capacity Enhancement with Relay Station Placement in Wireless Cooperative Networks Bin Lin1, Mehri Mehrjoo, Pin-Han Ho, Liang-Liang Xie and Xuemin (Sherman)
Automatic Evaluation of the Accuracy of Fixed-point Algorithms Daniel MENARD 1, Olivier SENTIEYS 1,2 1 LASTI, University of Rennes 1 Lannion, FRANCE 2.
Synchronization of Turbo Codes Based on Online Statistics
IEEE Transactions on Consumer Electronics, Vol. 58, No. 2, May 2012 Kyungmin Lim, Seongwan Kim, Jaeho Lee, Daehyun Pak and Sangyoun Lee, Member, IEEE 報告者:劉冠宇.
1. Adaptive System Identification Configuration[2] The adaptive system identification is primarily responsible for determining a discrete estimation of.
Image Coding/ Compression
Class Report 林常仁 Low Power Design: System and Algorithm Levels.
Class Report 何昭毅 : Voltage Scaling. Source of CMOS Power Consumption  Dynamic power consumption  Short circuit power consumption  Leakage power consumption.
An Energy Efficient Sleep Scheduling Considering QoS Diversity for IEEE e Wireless Networks Speaker: Wun-Cheng Li IEEE ICC 2010 Jen-Jee Chen, Jia-Ming.
Case Study: Implementing the MPEG-4 AS Profile on a Multi-core System on Chip Architecture R 楊峰偉 R 張哲瑜 R 陳 宸.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU CORDIC (COordinate Rotation DIgital Computer) For Advanced VLSI and VLSI Signal Processing.
Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms T. Arslan A.T. Erdogan S. Masupe C. Chun-Fu D. Thompson.
July 23, BSA, a Fast and Accurate Spike Train Encoding Scheme Benjamin Schrauwen.
ELEC692 VLSI Signal Processing Architecture Lecture 12 Numerical Strength Reduction.
L9 : Low Power DSP Jun-Dong Cho SungKyunKwan Univ. Dept. of ECE, Vada Lab.
NCTU, CS VLSI Information Processing Research Lab 研究生 : ABSTRACT Introduction NEW Recursive DFT/IDFT architecture Low computation cycle  1/2: Chebyshev.
Unit IV Finite Word Length Effects
CORDIC (Coordinate rotation digital computer)
CSI Feedback for Closed-loop MIMO-OFDM Systems based on B-splines
Distributed MIMO Patrick Maechler April 2, 2008.
Applications of Distributed Arithmetic to Digital Signal Processing:
Chapter 6 Discrete-Time System
A Comparative Study of Depth Map Coding Schemes for 3D Video
C Model Sim (Fixed-Point) -A New Approach to Pipeline FFT Processor
GSPT-AS-based Neural Network Design
Fixed-point Analysis of Digital Filters
Presentation transcript:

Area-Effective FIR Filter Design for Multiplier-less Implementation Tay-Jyi Lin, Tsung-Hsun Yang, and Chein-Wei Jen Department of Electronics Engineering National Chiao Tung University, Taiwan {tjlin, thyang,

In this paper We propose a complexity-aware quantization algorithm of FIR filters, which enables designers to explicitly trade quantization error for simpler implementations The proposed algorithm precisely distributes a pre-defined addition budget among the filter coefficients with successive approximation and common subexpression elimination

Outline Preliminary  Quantization by Successive Coefficient Approximation  Common Subexpression Elimination Complexity-Aware Coefficient Quantization Simulation Result Conclusion

Quantization by Successive Approximation* * D. Li, Y. C. Lim, Y. Lian, and J. Song, “A polynomial-time algorithm for designing FIR filters with power-of-two coefficients,” IEEE Trans. Signal Processing, vol.50, pp , Aug 2002

Constant Multiplications Consider a 4-tap FIR filter with the coefficients: h 0 = , h 1 = , h 2 = , and h 3 = Common Subexpression across Coefficients (CSAC)

Common Subexpression Elimination Tabular form CSAC CSWC

Steepest-descent CSE Heuristic* * M. Mehendale, S. D. Sherlekar, VLSI Synthesis of DSP Kernels - Algorithmic and Architectural Transformations, Kluwer Academic Publishers, 2001

Outline Preliminary Complexity-Aware Coefficient Quantization Simulation Result Conclusion

Complexity-Aware Quantization Complexity-aware allocation of non-zero terms (with CSE) Improved SF Exploration (next page)

Improved SF Exploration Instead of the fixed 2 -w stepping from the lower bound, the next SF is calculated as denotes the magnitude of a coefficient denotes the distance to its next quantization level as the SF increases, which depends on the approximation scheme (e.g. rounding to the nearest value, toward 0, or toward -∞, etc).

Simulation Result For 16-bit wordlength and ±3dB acceptable gain, the improved SF exploration has 14,986 to 20,429 candidates depending on the coefficients, instead of 45,875 for all. CSE Improved SF Search

Conclusion Successive approximation with appropriate scaling can significantly reduce the addition complexity The proposed algorithm controls the CSE to incur the minimum additions during the successive approximation The improved SF exploration finds better or identical (but never worse) results with only 1/3 candidates The proposed complexity-aware quantization algorithm allows designers to explicitly trade quantization error for simpler implementations, which can also be easily  modified for goals other than small area (e.g. low power, etc), or  adapted to other implementation styles (e.g. FIR code generation for programmable processors)