23 Jul 2008Paul Dauncey1 TPAC 1.1 vs TPAC2.0 vs TPAC2.1 Paul Dauncey

23 Jul 2008Paul Dauncey2 Overall aims Develop a technique not a technology (© Mike Tyndel) Aim to do an existence proof of a DECAL Doing a calorimeter experiment using CMOS sensors Not trying to design best CMOS sensor right now Need something which is “good enough” for the test Goals are To see whether a DECAL works at all (e.g. low energy photons) Check if performance agrees with expectations Get operational and analysis experience Find out where the limitations are so a better sensor could be designed in future Which effect is most important? Efficiency per pixel? Dead areas? Signal size? Charge diffusion between pixels? Pixel-to-pixel variations?

23 Jul 2008Paul Dauncey3 Resolution from MIP counting Better resolution by counting MIPs than energy deposits Removes fluctuations from Landau, angle and velocity Charge diffusion means one MIP can give between 1 and 4 pixel hits Need to cluster to get back to MIP count Essential but never tested with a real detector

23 Jul 2008Paul Dauncey4 What size stack? Tungsten-sensor stack of at least 15 layers (factor of two smaller than CALICE) Each layer with at least 10×10cm 2 coverage (factor of three smaller than CALICE) Energy resolution should be O(%) for higher energy EM showers Need to contain all the energy to this level to measure accurately There is also beam spread; has been at least 1cm in all CALICE beam tests 10% of peak 1% of peak

23 Jul 2008Paul Dauncey5 TPAC1.1 Submitted for fabrication this week Due back in late Sept Mainly a bug fix of the first TPAC Never intended to be usable in a beam stack for real shower measurements 168×168 pixels, 11% dead area within sensitive area TPAC1.1 has ~220 I/O wire bonds On all four sides of the sensor Cannot be flip-chip bonded Tiling a plane would be difficult…

23 Jul 2008Paul Dauncey6 TPAC2.0 and 2.1 If no Black December, then we would have had the money to make TPAC2.0 this year Realistic sensor for DECAL stack 3×2.5cm 2 area; 504×462 pixels, same 11% dead area ~100 I/O signals; flip-chip bondable (or wirebonds on two edges only) Control logic and serialized data readout Changes to pixel if found necessary from TPAC1.1 testing The only difference between TPAC2.0 and 2.1 is that the first is the prototype and the second production Rough cost is ~£120k for standard number of wafers plus £1.2k/wafer Could risk £180k on full production of TPAC2.0 without checking if sensor works first; would need another £180k if major error Have to assume redesign is needed when doing costing; both TD effort and fabrication TPAC2.0 design and basic test 1.5SY, TPAC2.1 is another 1SY

23 Jul 2008Paul Dauncey7 TPAC2 (cont) 12×12cm 2 layer covered by 5×4 array of TPAC2 sensors Total coverage 87%; dead areas small compared with shower core size ~10mm Total number needed 15×20=300 sensors (plus more to cover yield) Estimated cost for production ~£180k But would do prototype run first, costing ~£120k, so total is ~£300k

23 Jul 2008Paul Dauncey8 Cost-saving alternatives Use less area per layer Have some stack layers (at the front) with less sensors E.g. 5 layers of 2×2 sensors, 5 layers of 3×3 sensors and 5 layers of 5×4 sensor; totals 165 sensors (approx half) Cost of production ~£150k, so total ~£270k; saving ~£30k Use TPAC1.1 No redesign needed (assuming it works well enough) Use TPAC1.2 This is close to TPAC1.1 but with all wirebonds on two sides Would need to halve I/O signals; some design work on control and readout needed No flip-chip bonding development (Use Jessica Misses the point: not trying to design an optimal sensor, so this would incur a ~two year delay, with redesign costs, etc.)

23 Jul 2008Paul Dauncey9 TPAC1.1 stack Sensors are 1×1cm 2 and need a further 3mm stay-clear for wirebonds Example of covering 12×12cm 2 layer with TPAC1.1 with an 8×8 array of sensors Total coverage per layer would only be ~30%; using both sides would get ~55% Each PCB requires ~32k wirebonds Need 64×2×15~2000 sensors (plus more to cover yield) Estimated cost for 4000 sensors in shuttle run ~£250k, saving £50k Effort saving for TD 2.5SY (halves design “team”) and ~2SY RA effort

23 Jul 2008Paul Dauncey10 TPAC1.2 stack Sensors are still 1×1cm 2 but 3mm stay-clear only at sides Example of covering 12×12cm 2 layer with TPAC1.2 with an 12×12 array of sensors using both sides of PCB Each PCB requires ~18k wirebonds Total coverage per layer would be ~70% Need 144×15~2000 sensors (plus more to cover yield) Estimated cost for 4000 sensors in shuttle run ~£250k, saving £50k TD design effort ~1SY, saving 1.5SY, RA effort saving ~1SY