Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns

Introduction Cory

Introduction Flash Memory prevalence –Cell Phones, MP3 Players, Cameras, Hard Drives Still a new Technology –NAND flash memory has a limited number of read/write cycles, its behavior past this limit has not been widely analyzed Goals –Create a open source system to test NAND flash memory

BOM(Bill of Materials) FPGA BOARD VENDOR INFORMATION Altera contact: 357 S McCaslin Blvd, Louisville, CO F: P: Part # : DE2 DE2 Development & Education Board Time: 3-5 Days Price/Unit Cost: $ Quantity: 1 Total Cost: $269.00

BOM(Bill of Materials) Possible Alternative FPGA Digilent Inc. P.O. Box 428, Pullman, WA F: P: Part # : XUPV2P Virtex-II Pro Development System Time: 3-5 Days Price/Unit Cost: $ Quantity: 1 Total Cost: $299.00

BOM(Bill of Materials) NAND FLASH VENDOR INFORMATION Micron Technology contact: Dennis Z S Federal Way, Boise, ID F: P: Part # : 29F2G08AAC 2 Gbit w/ 8 bit I/O Time: 3-5 Days Price/Unit Cost: $0.00 Quantity: 6 Total Cost: $0.00 Provided by Micron

BOM (Bill of Materials) Software Components The following software components will be used to complete this project: TortoiseSVN subversion client – Free Download [7] Subclipse plugin for Eclipse/NIOS IDE – Free Download [8] Altera Quartus II Web Edition Verilog development environment – Free Download [9] Altera Nios II Embedded Design Suite – Free Download [9] LibUSBDotNet – C# LibUSB-Win32 wrapper for generic USB drivers – Free Download [5] Visual Studio IDE for C# GUI development – Provided by MSDNAA [10] Microsoft SQL 2008 Server - SQL database engine to store results - - MS SQL Express – Provided by MSDNAA [11]

Daughter Board / Memory Controller and FPGA Jake

FPGA Altera DE2 Development Board –NIOS II processor –Runs C code –Interfaces USB (for communication with the computer) IDE (for communication with the Daughter Board)

FPGA System On A Programmable Chip –Components are modularly programmed and developed FPGAs USB doesn’t need to know the specifics of the Daughterboard Internal components communicate over the Avalon Bus –The SOPC builder tool helps to automate the integration process

Integration The Avalon bus on the Altera FPGA allows segmentation of the various components –USB controller –Flash memory controller –GUI Each component can be developed separately without majorly affecting the other components and integrated with other components at a later date

Daughter Board Contains the 48-pin TSOP socket where the flash memory chip is tested. Communicates with FPGA through an IDE cable (but not using IDE interface)

NAND Memory Controller Responsible for writing and reading from NAND chip –Generates appropriate write signals timing of these signals is very important –Reads the responses from the NAND chip –Writes results directly into RAM (shared memory model) –Designed by last year’s team

USB interface Sze

USB interface LibUSBDotNet –Open source USB interface libraries Coded in C# Much easier that programming a full windows driver –Last years team had trouble getting USB working because they were trying to write their own USB driver

USB interface FPGA USB interface –Communicates with the host PC –Is programmed in firmware –Responsible for: receiving commands from the host PC Transmitting results to the host PC

USB interface Usb interface on host PC stores results in a SQL database –using the ActiveX Data Objects Classes of the.NET framework to communicate with the database Normalized database T-SQL (Transactional SQL) –extension to the SQL database programming language Initially SQL database will store basic info but can be expanded

Graphical User Interface on the PC and Risks Mike

Graphical User Interface on the PC Running tests –The GUI will allow the user to program a series of tests to run on the flash memory Commands –Read page and Verify –Program a page –Erase a block and check for failures Automated Testing patterns can be specified –range of blocks to test –Number of cycles to run for –Can use specific memory patters or randomly generated patterns for testing.

Graphical User Interface on the PC Memory testing patterns –RAM test patterns do not work well for testing flash memory (March pattern) Example: writes or reads cause cells in a different cell to be changed. –Need to choose testing patterns that solicit these types of failures 5n

Graphical User Interface on the PC Viewing Results –See raw data Sometime necessary –Display Graphs of data Allow the user to see trends over time –examples Flash memory is unreliable after X cycles Certain blocks of memory are more susceptible to failure than others

Conclusion Hartman

Risks Previous team( ) was unable to get full system working. They were only able to get the interface between the daugterboard and the fpga operational We will need to test and debug their interface for full functionality

Risks The previous team was unable to get USB working properly We may still have significant issues with usb connections –Hopefully using libusbdotnet will solve this

Risks We will need to complete quickly enough so that we can run tests on memory and determine failure patterns and rates

Implementation Timeline

Conclusion Using data generated by the FLAP platform it will be possible to: –Determine the best ECC algorithms –How many spare blocks per chip are necessary –Predict failure rates for specific use patterns (server vs. workstation use, etc)