ELEC 301 Spring 2009 VOLKAN KURSUN ELEC 301 Introduction Volkan Kursun

ELEC 301 Spring 2009 VOLKAN KURSUN Motivation: Why CMOS VLSI Design?  The developments in nanoelectronics and VLSI design are critical for a stronger world economy  The annual revenues of semiconductor industry approach US$300 billion  Integrated circuits are in 95% of every electrically powered device in the world  Integrated circuits are the basic building blocks of devices such as cell-phones, MP3/MP4 players, and notebook computers: key technology to sustain a modern society

ELEC 301 Spring 2009 VOLKAN KURSUN Motivation: Where is the Money?  2008 total annual revenues of semiconductor industry ~US$262 billion *

ELEC 301 Spring 2009 VOLKAN KURSUN Why VLSI Design ?  Building complex electronic circuits integrated onto a single piece of silicon  Using discrete components is difficult and costly  Integrated circuits solve much of the problems  Print many small devices on a flat surface  More reliable  Lower cost  VLSI is a relatively new field  Started early 60’s

ELEC 301 Spring 2009 VOLKAN KURSUN Anything New in IC Design?  Why is designing digital ICs different today than it was before?  Will it continue to change in the future?  Isn’t there an enough number of IC design engineers who already know everything?

ELEC 301 Spring 2009 VOLKAN KURSUN The First Computer

ELEC 301 Spring 2009 VOLKAN KURSUN ENIAC - The first electronic computer (1946)

ELEC 301 Spring 2009 VOLKAN KURSUN The Transistor Revolution First transistor Bell Labs, 1948

ELEC 301 Spring 2009 VOLKAN KURSUN Historical Developments  (1) In 1951, Shockley developed the junction transistor  In 1954, TI made the first silicon transistor (2.5$)  In 1959, Jack Kilby of Texas Instruments invented the first hybrid-integrated circuit  (2) Robert Noyce of Fairchild invented the first monolithic IC in 1959  (3) The first semi-custom chip marketed by Fairchild in 1967 (1.) (2.)(3.)

ELEC 301 Spring 2009 VOLKAN KURSUN Technology Scaling and Moore’s Law Transistors sizes shrink by 30% per generation Chips become larger With every generation the number of transistors integrated on a chip can be increased  In 1965, Gordon Moore of Fairchild noted that the number of transistors on a chip doubled every 18 to 24 months l He made a prediction that this trend would continue into the foreseeable future

ELEC 301 Spring 2009 VOLKAN KURSUN Moore’s Law Electronics, April 19, 1965.

ELEC 301 Spring 2009 VOLKAN KURSUN Following Moore’s Law: Moore’s Move l In 1968, Gordon Moore and Robert Noyce left Fairchild and founded Intel l Initial idea was to capitalize on the new IC technology with a new company that specializes on memory chips

ELEC 301 Spring 2009 VOLKAN KURSUN Did Moore and Noyce Succeed? Where is the Money? *

ELEC 301 Spring 2009 VOLKAN KURSUN Intel Chips  (4): The first memory chip marketed by Intel in 1970: The 1103 IC contained 1K RAM  The same year Intel decides to get out of the memory market  (5): In 1971 Intel introduced the first microprocessor  The 4004 had 2300 tr built in a 10  m process and operates with 4-bit precision at 108KHz  (6): 80-core Intel Polaris Processor (2007) (4) (5)(6) Teraflop: floating point operations per second

ELEC 301 Spring 2009 VOLKAN KURSUN Evolution in Memory Complexity

ELEC 301 Spring 2009 VOLKAN KURSUN Moore’s law in Microprocessors Pentium® proc P Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Die Size Growth Pentium ® proc P Year Die size (mm) ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Frequency P6 Pentium ® proc Year Frequency (Mhz) Lead microprocessor frequency used to double every 2 years Doubles every 2 years Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead microprocessors power continued to increase over the years Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Power is a major problem 5KW 18KW 1.5KW 500W Pentium® proc Year Power (Watts) Power delivery and dissipation are prohibitive Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Battery Lifetime in Portable Applications Digital Cellular Market (Phones Shipped) Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone

ELEC 301 Spring 2009 VOLKAN KURSUN Power Density and Cooling Challenges Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density is too high to maintain low junction temperature Courtesy, Intel

ELEC 301 Spring 2009 VOLKAN KURSUN Challenges in Digital Design “Microscopic Challenges” Ultra-high speed design More functionality Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution Everything Looks a Little Different “Macroscopic Issues” Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability …and There’s a Lot of Them!  DSM  1/DSM ? Solution: More Moore?????

ELEC 301 Spring 2009 VOLKAN KURSUN Design Metrics  How to evaluate the performance of a digital circuit?  Cost (everything is “for a few dollars more”*)  Scalability  Reliability  Speed –Delay, operating frequency  Power dissipation  Energy to perform a function

ELEC 301 Spring 2009 VOLKAN KURSUN Cost of Integrated Circuits  Fixed costs  NRE (non-recurrent engineering) costs  Independent of the number of products sold –Design time and effort –Mask generation  One-time cost factor

ELEC 301 Spring 2009 VOLKAN KURSUN NRE Cost is Increasing

ELEC 301 Spring 2009 VOLKAN KURSUN Cost of Integrated Circuits  Variable costs  Recurrent costs  Dependent on the product volume  Dependent on the chip area –Costs of silicon processing, packaging, and testing

ELEC 301 Spring 2009 VOLKAN KURSUN Wafer size Single die Wafer From Going up to 12” (300mm)  Has been steadily increasing over the years  Yields more dies per wafer  Directly determines the cost of a die

ELEC 301 Spring 2009 VOLKAN KURSUN Trend for Larger Wafers  8086s were built on a 50mm (diameter) wafer  Latest Pentiums and Itaniums are built on a 300mm wafer Intel Pentium4 wafer Intel Itanium wafer

ELEC 301 Spring 2009 VOLKAN KURSUNDefects  is approximately 3  Manufacturing process is not perfect  Faults are introduced

ELEC 301 Spring 2009 VOLKAN KURSUN Yield

ELEC 301 Spring 2009 VOLKAN KURSUN  Increasing die area increases the cost  Fewer ICs come out of a single wafer  Higher chances for a defective die  The smaller the devices  The higher the integration density  The smaller the die size –Lower cost  The higher the speed –Reduced parasitic impedances and higher current  The lower the power consumption  These are why the technology scaling is the key  Moore’s economic model Die Size

ELEC 301 Spring 2009 VOLKAN KURSUN Cost per Transistor – Essence of Moore’s Law  Transistors become more plentiful and cheaper over time No Exponential is Forever...but We Can Delay 'Forever' Gordon E. Moore, presentation at International Solid State Circuits Conference (ISSCC), February 10, 2003

ELEC 301 Spring 2009 VOLKAN KURSUN Consequences of Technology Scaling  Transistors become smaller every technology generation  With every generation more transistors can be integrated on a chip to enhance functionality and performance  Per transistor cost decreases  However …  How to cope with the increased design complexity?  Design engineering population does not double every two years…

ELEC 301 Spring 2009 VOLKAN KURSUN Productivity Trends ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap Hence the need for more efficient design methodologies and better circuit and system designers Exploit different levels of abstraction

ELEC 301 Spring 2009 VOLKAN KURSUN Design Abstraction Levels n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM

ELEC 301 Spring 2009 VOLKAN KURSUN  Many disciplines have contributed to this spectacular technological development:  Solid-state devices- Circuit design  Lithography and fabrication- Architecture and algorithms  Modeling  Computer-Aided-Design (CAD) tools  ELEC301 focuses on the following topics:  Modeling of FETs, digital circuit design, and layout  CAD tools (full-custom design)  Other topics are studied in other courses:  ELEC304: Analog IC, ELEC506: Semiconductor devices, ELEC516 Digital system design Actors of Technological Development

ELEC 301 Spring 2009 VOLKAN KURSUN What Are We Going to Learn in ELEC301?? Technological choice CMOS Technology CMOS design tool CADENCE Level of abstraction Specification, architecture, logic design, layout design Hierarchical design Will be used in the project Challenges Conflicting objectives, Short design time Type of integration Full-Custom

ELEC 301 Spring 2009 VOLKAN KURSUN –Hierarchy involves dividing a module into sub-modules. – The operation is repeated on the sub-modules until the complexity of the sub-modules is at an appropriately manageable level of detail Hierarchical Design cell A cell C cell B cell D cell E cell A cell B cell C cell D cell E Hierarchy level Level 0 Level 1 Level 2 cell1 –Due to the hierarchy property, when a cell is modified, all other links are changed simultaneously

ELEC 301 Spring 2009 VOLKAN KURSUN Circuit and System representations Specification Behavior Register-transfer Logic Circuit Layout Executable Program, VHDL Sequential Machines Logic Gates Transistors Rectangles Behavioral Domain Structural Domain Physical Domain Structural Domain Behavioral Domain Functionality Top-Down design methodology: Before drawing the layout (last step) you need to check the functionality, logic and transistor level description

ELEC 301 Spring 2009 VOLKAN KURSUN  Goal  Reduce the design time  Complexity management (millions of cells and billions of transistors cannot be handled manually)  The tools  Cadence - Synopsys  Mentor Graphics  HSpice  Why software are always updated and modified ?  To cope with advanced new technologies  To cope with new design flow/methodology for new type of design philosophy for ever-increasing complexity of the chips  To cope with increasing complexity of integrated circuits  To satisfy the requirements of a mixed analog-digital design and mixed mode design methodologies such as Full-custom;Std cell CMOS VLSI Design: The Tools

ELEC 301 Spring 2009 VOLKAN KURSUN Computer Aided Design (CAD) Tools  Synthesis tools to synthesis complex circuit from a behavior description  Standard Cell place and route for fast digital semi- customer design  Symbolic layout tools to ease the task of physical design, mask verification (DRC) to ensure manufacturability  Circuit analysis programs predict circuit all the process corners. Gate level and behavioral simulators help to get it right the first time  Tools to do the repetitive work such as routing or verifying that the layout and schematic match (LVS)  The design needs to be performed following a design flow

ELEC 301 Spring 2009 VOLKAN KURSUN Different CMOS Design Styles  SOC (System-on-chip) Design  Many different views  SOC is a system on an IC that integrates software and hardware Intellectual Property (IP) using more than one design methodology to define/design the functionality and behavior  Application-specific IC  Usually semi-custom design using a lot of automated tools (automatic synthesis)  Full custom IC  High-performance oriented  Analog or mixed signal  This course will mainly focus on full-custom design

ELEC 301 Spring 2009 VOLKAN KURSUN Full-Custom Design  Start from individual transistors and build-up  Customize and optimize everything Customize: to build, fit, or alter according to individual specifications From optimized individual transistors and gates to a billion transistor chip: Is it feasible?

ELEC 301 Spring 2009 VOLKAN KURSUN  Possibility of automatic placement and routing  Need large variety of cells  Short design time  Security of the results  Economical  Possible optimization and hence more performance  Total conception  Time consuming  Less secure results  Costly Standard Cell Full Custom - For digital-circuit designs, many basic logic gates are used repeatedly. Thus, to save time, the designers build up a library of logic gates, and they utilize the logic gate layouts repeatedly. The layouts of the logic gates inside a design library are called standard cells. -Placement and routing strategy is then used. - The standard cells are not optimized since they are realized in order “to fit” the most of digital application. In order to improve the performance for a given application, a full-custom approach is preferred Choice of Design Methodology

ELEC 301 Spring 2009 VOLKAN KURSUN Standard Cell Based Design Placement involves finding the most suitable arrangement in the 2D plane for the cells in the design. Routing solves the non-planar interconnection problem created by the placement. From layout, actual transistor sizes and capacitance may be calculated. Simulations may again be run to confirm behavior at required speed and estimate power dissipation. For each standard cell, the cell height is the same, and this can provide direct connections for VDD and GND. VDD GND inv nand2 nor2regnor2 invnand2nor2muxinvmux Routing Channels

ELEC 301 Spring 2009 VOLKAN KURSUN Summary of IC Design Process